To detect air in a fluid delivery line of an infusion system, infusion fluid is pumped through a fluid delivery line adjacent to at least one sensor. A signal is transmitted and received using the at least one sensor into and from the fluid delivery line. The at least one sensor is operated, using at least one processor, at a modified frequency which is different than a resonant frequency of the at least one sensor to reduce an amplitude of an output of the signal transmitted from the at least one sensor to a level which is lower than a saturation level of the analog-to-digital converter to avoid over-saturating the analog-to-digital converter. The signal received by the at least one sensor is converted from analog to digital using an analog-to-digital converter. The at least one processor determines whether air is in the fluid delivery line based on the converted digital signal.

In an analog-to-digital converter circuit, a sum output unit calculates the sum of an n-bit data value outputted from a first output unit and an (n + 1)-bit data value outputted from a second output unit to accordingly obtain the calculated sum as a digital data value. A second calculator of the second output unit calculates the sum of a sign bit of a third digital data value as a most significant bit thereof and a second significant bit of the third digital data value. The combines a bit selected from the calculated sum with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n + 1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum.

A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

A real-time digital sparkle filter for processing high-speed analog to digital converter (ADC) data is disclosed. The real-time digital sparkle filter for processing a continuous stream of digital data, comprising a high-speed data interface, a digital sparkle filter, and a buffer sequencer. The high-speed data interface receives sample data from an analog to digital converter (ADC). The digital sparkle filter operates continuously on the sample data without losing any samples. The digital sparkle filter comprises one or more logic implemented using field-programmable gate arrays (FPGAs) configured to continuously process the data without degrading the signal content. The buffer sequencer comprises an input buffer and an output buffer. The input buffer receives the digital data stream data using a first in first out buffer mechanism. The output buffer receives the processed output of the sparkle filter, thereby eliminating the sparkle noise without degrading data content.

An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

An integrated circuit (IC) includes an analog to digital converter (ADC) circuit having an ADC input and an ADC output. The ADC circuit is configured to receive an input signal at the ADC input and generate a digital output signal at the ADC output based on the input signal. An ADC circuit path is coupled between the ADC input and the ADC output. The ADC circuit comprises a plurality of capacitors coupled between reference voltage sources and the ADC circuit path. The ADC has a reconfigurable resolution and a reconfigurable sampling rate. The ADC circuit is configured to scale the reference voltage sources and/or the plurality of capacitors based on the reconfigurable resolution.

A signal processing device includes a first adjuster, a second adjuster, and a digitizer. The first adjuster coarsely adjusts an output range of a signal input to the first adjuster to output a first signal. The second adjuster adjusts an output range of a signal more finely than the first adjuster adjusts to output a second signal. The digitizer digitizes the first signal or the second signal to output a digital signal. The digital signal has an output range of a signal that is finely adjusted with the second adjuster after being coarsely adjusted with the first adjuster.

A solid-state imaging apparatus of this invention includes an output unit that outputs an analog signal, and an offset addition unit that, in a case where the analog signal is out of a range in which A/D conversion is possible in the A/D conversion unit, adds an offset to the analog signal in the output unit so that the analog signal is not out of the range in which A/D conversion is possible.