A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.

A method for light-to-digital conversion includes setting a time integrator circuit into a reference condition and starting to integrate charge from a sensor device for the duration of an integration time. An integration signal is generated and is indicative of the integrated charge. The integration signal is compared with an adjustable reference signal. A first count is generated when the comparison indicates that the integration signal has reached an integration range, wherein the integration range is defined by a low and a high voltage. A second count is generated when the comparison indicates that the integration signal has reached the adjustable reference signal. The adjustable reference signal is incremented in discrete steps when a second count has been generated. Then, the time integrator circuit is reset into the reference condition, when the comparison indicates that the integration signal has reached the integration range. The generated first counts is collected as first count signal and the generated second counts are collected as second count signal. Finally, a digital output signal is generated depending on the first count signal and the second count signal.

An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

An analog-to-digital conversion circuit includes a convertor configured to perform a first comparison operation for sensing a noise based on a reset signal and to perform a second comparison operation for sensing raw data to output data which is obtained by removing the noise from the raw data, and a ramp voltage generator configured to generate a ramp voltage used for the first comparison operation and the second comparison operation and to output the ramp voltage to the convertor. The ramp voltage generator includes a first current source for supplying a bias current for generating the ramp voltage in response to a first control signal, a second current source for supplying a boost current for generating the ramp voltage in response to a second control signal, and a generation circuit for generating the ramp voltage based on the bias current and the boost current.

An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage V.sub.BIAS with respect to a CM voltage V.sub.CM. The CM voltage V.sub.CM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

An image sensor may include an array of image sensor pixels that are read out using analog-to-digital converters (ADCs). The ADC may be shot-noise-matched to reduce the number of decision cycles required. A ramp with limited resolution spanning only a small portion of the full scale voltage range may be used. For small analog input voltages, this limited ramp range is sufficient. For large analog input voltages, less resolution is needed due to the increasing shot noise in the photo signal. The larger input voltages may be successively divided by a selected attenuation factor until the analog input signal is within the range of the reduced ramp. The ADC keeps track of the number of divisions being performed to determine an exponent value for a floating-point output value and then convert the residual signal with the smaller ramp to determine a mantissa value for the floating-point output value.

The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

An A/D conversion device, which operates in one mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

A method for light-to-digital conversion includes setting a time integrator circuit into a reference condition and starting to integrate charge from a sensor device for the duration of an integration time. An integration signal is generated and is indicative of the integrated charge. The integration signal is compared with an adjustable reference signal. A first count is generated when the comparison indicates that the integration signal has reached an integration range, wherein the integration range is defined by a low and a high voltage. A second count is generated when the comparison indicates that the integration signal has reached the adjustable reference signal. The adjustable reference signal is incremented in discrete steps when a second count has been generated. Then, the time integrator circuit is reset into the reference condition, when the comparison indicates that the integration signal has reached the integration range. The generated first counts is collected as first count signal and the generated second counts are collected as second count signal. Finally, a digital output signal is generated depending on the first count signal and the second count signal.