An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n−1).sup.th differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a n.sup.th differential signal pair among the n differential signal pairs.

An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n−1).sup.th differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a n.sup.th differential signal pair among the n differential signal pairs.

A processing system with a microarchitectural feature for mitigation of differential power analysis and electromagnetic analysis attacks can include a memory, a processor, and a mitigation response unit. The processor can include an instruction predictor that comprises a storage device for storing metadata associated with corresponding instruction blocks. The mitigation response unit is coupled to the instruction predictor to write and read the metadata associated with the corresponding instruction blocks. The mitigation response unit is configured to determine a mitigation technique for an instruction block based on an electromagnetic or power signature corresponding to execution of the instruction block and metadata associated with the instruction block.

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

In an embodiment a method includes providing an analog signal comprising a first value of a temperature of an object, performing an analog-to-digital conversion of the analog signal using a first analog-to-digital converter (ADC) thereby providing a first digital signal representing an initial digital temperature value, performing an analog-to-digital conversion of the analog signal using a second ADC thereby providing a second digital signal representing a digital reference temperature value, regularly providing the analog signal comprising a successive value of the temperature of the object, performing the analog-to-digital conversion of the analog signal using the second ADC thereby providing the second digital signal representing a successive digital temperature value, calculating a digital delta temperature value according to a difference between the successive digital temperature value and the digital reference temperature value and repeating providing the analog signal, performing the analog-to-digital conversion and calculating the digital delta temperature value as long as the digital delta temperature value lies within a predefined range.

A method for light-to-frequency conversion comprises generating a photocurrent by means of a photodiode and converting the photocurrent into a digital comparator output signal in a charge balancing operation depending on a first clock signal. From the digital comparator output signal an asynchronous count is determined and comprises an integer number of counts depending on the first clock signal. From the digital comparator output signal a fractional time count is determined and depends on a second clock signal. Finally, from the asynchronous count and from the fractional time count a digital output signal is calculated which is indicative of the photocurrent generated by the photodiode. The method may be carried out by an exemplary light-to-frequency converter equipped with a photodiode.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

A current detection circuit, a semiconductor device and a semiconductor system which are capable of improving current detection accuracy are provided. According to one embodiment of the invention, a current detection circuit includes a resistive element to convert an input current supplied from outside into an input voltage, a constant-current source, a resistive element to convert an output current of the constant-current source into a reference voltage, and an AD converter to AD-convert the input voltage using the reference voltage.