Patent classifications
H03M1/181
DIFFERENTIAL CONVERTER WITH OFFSET CANCELATION
In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.
Tracking analog-to-digital converter with adaptive slew rate boosting
A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.
Control device, switching converter and method for controlling an output variable
A digital closed loop control system. An output signal is detected with the aid of an analog-to-digital converter. A correction value is subtracted from the output signal prior to the analog-to-digital conversion and this correction value is added up again after the analog-to-digital conversion. The correction value in this case may be dynamically adapted. In this way, the analog-to-digital converter may be operated in a narrow conversion range.
DIGITAL CONTROL REGULATOR
Provided is a low voltage and compact digital control regulator that achieves enhanced stability and reduced variations in ripple voltage and droop characteristics. The digital control regulator includes a first A/D converter configured to generate a first digital signal according to a differential voltage between an output voltage and a first reference voltage, an output stage circuit configured to generate the output voltage, a replica circuit having the same circuit configuration as the output stage circuit and configured to output a replica voltage related to the output voltage, a second A/D converter configured to generate a second digital signal according to a differential voltage between the replica voltage and a second reference voltage, and a control circuit configured to generate a control signal for controlling a gain of the output stage circuit, according to the first digital signal and the second digital signal.
ADAPTIVE ANALOG TO DIGITAL CONVERTER (ADC) MULTIPATH DIGITAL MICROPHONES
Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.
CONTROL DEVICE, SWITCHING CONVERTER AND METHOD FOR CONTROLLING AN OUTPUT VARIABLE
A digital closed loop control system. An output signal is detected with the aid of an analog-to-digital converter. A correction value is subtracted from the output signal prior to the analog-to-digital conversion and this correction value is added up again after the analog-to-digital conversion. The correction value in this case may be dynamically adapted. In this way, the analog-to-digital converter may be operated in a narrow conversion range.
MAGNETORESISTIVE ASYMMETRY COMPENSATION
Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.
Dynamic control of sensitivity associated with detecting R-waves
Devices and methods for dynamically controlling sensitivity associated with detecting R-waves while maintaining the fixed detection threshold are described herein. One such method includes sensing an analog signal indicative of cardiac electrical activity, converting the analog signal indicative of cardiac electrical activity to a digital signal indicative of cardiac electrical activity, and detecting R-waves by comparing the digital signal indicative of cardiac electrical activity to a fixed detection threshold to thereby detect threshold crossings that corresponds to R-waves. The method further includes selectively adjusting a gain applied to the digital signal indicative of cardiac electrical activity to thereby selectively adjust a sensitivity associated with the detecting R-waves, while maintaining the fixed detection threshold.
Differential converter with offset cancelation
In described examples, a sample and hold circuit is configured to periodically connect one input of an op-amp to a reference voltage through a switch while a second input of the op-amp is connected to an output of the op-amp. Offset cancellation is performed by storing a sampled offset on a sampling capacitor coupled to the second input of the op-amp.
SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
A solid-state imaging device that is capable of improving an imaging characteristic by enhancing a dynamic range of an ADC is provided. A solid-state imaging device (11) that includes a pixel array (12) including a plurality of pixels outputting a pixel signal by photoelectric conversion; and an AD conversion processing unit (30) that performs AD conversion with respect to the pixel signal, and in which the AD conversion processing unit includes a comparator having a first amplifying unit (81) that includes a pair of first differential pairs constituted of P-type transistors and a pair of second differential pairs constituted of N-type transistors; and a second amplifying unit (82) that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series is provided.