The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

This disclosure relates to a feedback loop circuit for an electrical signal. The feedback loop comprises a first branch having a first switch and a second switch, the first branch to receive an input signal and provide a first signal based on the input signal to a first adder and to provide a second signal based on the input signal to a second adder; and a second branch having a feedback line coupled between a third switch and the first adder, the second branch to provide an output signal based on the first signal and the second signal.

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.

An example apparatus includes a windowing component. The windowing component may set a first voltage level as an upper bound for a voltage window and set a second voltage level as a lower bound for the voltage window. The windowing component may modulate an input signal to have a maximum magnitude less than the upper bound for the voltage window and a minimum magnitude greater than the lower bound for the voltage window.

In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

This application relates to methods and apparatus for voltage regulation. Embodiments relate to signal processing circuit (300) having a first and second processing path with respective first and second inputs (INP and INN). The first and second processing paths have respective first and second virtual earth nodes (108P and 108N) at the input to a differential integrator (106). A differential feedback path is configured to apply a feedback signal to each of the first and second virtual earth nodes so as to minimize any voltage difference between them. A regulator (301) is operable to monitor a voltage at one of the virtual earth nodes (108P) against a reference voltage (V.sub.REF) and to generate a regulation signal to maintain the voltage at said monitored one of the first and second virtual earth nodes to be equal to the reference voltage. The regulation signal is applied to both of the first and second virtual earth nodes.

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.