An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M<B.

An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M<B.

Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

A device comprises an integrated circuit (IC) die, a substrate, a printed circuit board (PCB), an antenna, and a waveguide stub. The IC die is affixed to the substrate, which comprises a signal launch on a surface of the substrate that is configured to emit or receive a signal. The substrate and the antenna are affixed to the PCB, such that the signal launch and a waveguide opening of the antenna are aligned and comprise a signal channel. The waveguide stub is arranged as a boundary around the signal channel. In some implementations, the waveguide stub has a height of λ/4, where λ represents a wavelength of the signal. In some implementations, the antenna includes the waveguide stub; in others, the substrate includes the waveguide stub.

A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.

A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.

An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.