A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

To prevent occurrence of an input voltage dependent error due to an input parasitic capacitance. A comparator includes: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair; a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; and a fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

A device configured to monitor a voltage at a voltage rail for driving a motor includes processing circuitry configured to receive an indication of a switching signal for a phase of a plurality of phases of the motor. Inverter circuitry associated with the device is configured to electrically couple the phase to the voltage rail or to a reference rail associated with the voltage rail based on a driving signal that is generated based on the switching signal. The processing circuitry is further configured to determine a measurement time to measure the voltage at the voltage rail based on the switching signal and generate, using an analog-to-digital converter (ADC), a set of measured voltage values based on the voltage at the voltage rail during the measurement time.

Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

An imaging device of the present disclosure includes: a plurality of pixel circuits that each generates a pixel signal including a pixel voltage corresponding to an amount of received light, and performs AD conversion by comparing the pixel signal with a reference signal; and a reference signal generator including a signal generation circuit and a voltage follower circuit, the signal generation circuit that generates a voltage signal having a ramp waveform, and the voltage follower circuit that performs a voltage follower operation on the basis of the voltage signal to generate the reference signal, and supplies the reference signal to the plurality of pixel circuits.

An imaging device of the present disclosure includes: a plurality of pixel circuits that each generates a pixel signal including a pixel voltage corresponding to an amount of received light, and performs AD conversion by comparing the pixel signal with a reference signal; and a reference signal generator including a signal generation circuit and a voltage follower circuit, the signal generation circuit that generates a voltage signal having a ramp waveform, and the voltage follower circuit that performs a voltage follower operation on the basis of the voltage signal to generate the reference signal, and supplies the reference signal to the plurality of pixel circuits.