Time-to-digital conversion circuitry converts a time between a start time point and a stop time point, which are state-change time points of digital signals, into digital. The time-to-digital conversion circuitry comprises oscillation circuitry that outputs a plurality of phase signals having different phases, and outputs a digital value of the time based on the plurality of phase signals. The oscillation circuitry performs free-running oscillation and outputs the phase signals that do not synchronize with the start time point and the stop time point.

An A-D conversion circuit configured to convert an analog input signal into numerical data using a pulse delay circuit includes pulse position digitizing units, a clock generation circuit, and a processing unit. The clock generation circuit includes inverters each including one or more n-channel transistors and one or more p-channel transistors. The inverters differ from each other in a number ratio of the number of n-channel transistors connected in a common-gate parallel-connected manner and the number of p-channel transistors connected in a common-gate parallel-connected manner.

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

An A/D conversion circuit converts an analog signal into numerical data. The A/D conversion circuit includes: a pulse delay circuit that includes an odd number of delay units connected in series, and inverting and delaying a pulse signal, and that changes the numeral number of the delay units which the pulse signal passes through in accordance with a value of the analog signal; latch circuits that synchronize the pulse signal with sampling clocks, and latch the pulse signal; encoders that set a position of the pulse signal to the numerical data by circulating encode values periodically set in order from an initial value to a final value to synchronously sample the encode values; subtractors that calculate each of differences between a previous value and a current value; and an adder that adds subtraction results. The encode values are set to be shifted between at least two encoders.

A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2.sup.n(2m1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2.sup.n+(2m1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and nm. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.

Time-to-digital conversion circuitry converts a time between a start time point and a stop time point, which are state-change time points of digital signals, into digital. The time-to-digital conversion circuitry comprises oscillation circuitry that outputs a plurality of phase signals having different phases, and outputs a digital value of the time based on the plurality of phase signals. The oscillation circuitry performs free-running oscillation and outputs the phase signals that do not synchronize with the start time point and the stop time point.

An A/D converter circuit that converts analog information to numerical data is provided with a pulse delay circuit and an output unit. A sampling period is set so that a relationship between the sampling period and a circulation period of a pulse signal passing through a ring delay circuit satisfies a relational expression Trdln<Ts Trdl(n+1). In the relational expression, Ts is the sampling period, Trdl is the circulation period in which the pulse signal circulates through the pulse delay circuit, and n is an integer equal to or greater than 0.

A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.