A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes first delay units connected in series by (2.sup.n-(2m1)), and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes second delay units connected in series by (2.sup.n+(2m1)), and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and nm. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units.

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units.

A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.