A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.

In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

In one or more embodiments, an efficient scheme is provided for sampling inductor currents in a digital multiphase PWM controller used for high-bandwidth voltage regulation. Some embodiments use the data from the PWM modulator along with weighted states based on the PWM waveform and past conversions in order to prioritize which current sense input should be sampled for each conversion. In these and other embodiments, a single ADC is used to sample inductor currents from two or more phases in a multiphase PWM controller, thereby providing power and area savings, for example.

Demodulation circuitry includes an input terminal configured to be coupled to an analog-to-digital converter (ADC) and configured to receive a plurality of ADC outputs. The plurality of ADC outputs are generated based on resolver outputs. The demodulation circuitry also includes a rectifier configured to rectify the plurality of ADC outputs. Rectifying the plurality of ADC outputs preserves a phase of the plurality of ADC outputs. The demodulation circuitry includes amplitude determination circuitry configured to determine, based on the rectified plurality of ADC outputs, demodulated amplitude values corresponding to the resolver outputs. The demodulation circuitry further includes angle computation circuitry configured to generate position outputs based on the demodulated amplitude values.

An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

A signal amplifier includes a pulse width modulator, a level shifter, and a power amplifier. The pulse width modulator is driven by a positive power supply and a negative power supply, and a reference voltage of the pulse width modulator is set to a GND. The power amplifier is driven by a positive power supply, and a reference voltage of the power amplifier is set to a middle value between the positive power supply and the GND. The level shifter shifts a voltage level of a first PWM signal whose high level corresponds to the positive power supply of the pulse width modulator and whose low level corresponds to the negative power supply of the pulse width modulator, to a voltage level of a second PWM signal whose high level corresponds to the positive power supply of the power amplifier and whose low level corresponds to the GND.

Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.

A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (S.sub.IN) at an input node (102) and outputs a corresponding time-encoded signal (S.sub.OUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (S.sub.IN) to the feedback signal (S.sub.FB) with hysteresis. This provides a pulse-width modulated output signal (S.sub.OUT) where the duty cycle encodes the input signal (S.sub.IN).

A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.