A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.

A novel non-uniform sampling technique for a burst type signal. The analog signal is digitized with high sampling rate to maintain harmonics at higher frequencies and consequently the integrity of the analog signal. Then by using non-uniform sampling technique the most significant samples are selected for further processing which results in overall cost and power consumption reduction.

Facilitating a reduction in sensor system latency, circuit size, and current draw utilizing a group of continuous-time Nyquist rate analog-to-digital converters (ADCs) in a round-robin manner is presented herein. A sensor system can comprise a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system; a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors; a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; and a continuous-time Nyquist rate analog-to-digital converter of the group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system.

According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

The present application discloses an analog-to-digital conversion (ADC) circuit. The circuit includes an integral circuit including an operational amplifier and an integral capacitor. The circuit further includes a comparator and a timer. The operational amplifier includes a positive input terminal configured to receive a first voltage, a negative input terminal coupled to a signal-collection line configured to collect an analog current signal, and an output terminal configured to output a first output signal. The comparator is configured to compare the first output signal with a second voltage to generate a second output signal to the timer. The timer is configured to start a timing operation when the operational amplifier receives the analog current signal and end the timing operation when the second output signal changes. A binary data resulted from the timing operation characterizes a digital signal corresponding to the analog current signal.

This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.

An analog-to-digital converter (ADC) includes an analog voltage sampler having an energy storage device, such as a capacitive element, configured to charge based on an analog input voltage. A timer determines an elapsed time for the energy storage device to discharge to a predetermined value. The ADC outputs a digital value representing the analog input voltage based on the determined elapsed time.

Techniques are disclosed for analog-to-digital conversion systems and methods with pulse generators. In one example, an imaging system includes an analog-to-digital converter (ADC). The ADC includes a comparator configured to generate a comparator output signal based on a first signal and a second signal. The comparator output signal is associated with a first state or a second state. The ADC further includes a pulse generator coupled to the comparator. The pulse generator is configured to generate a pulse signal in response to a transition of the comparator output signal from the first state to the second state. The ADC further includes a memory device coupled to the pulse generator. The memory device is configured to capture a counter value from a counter circuit in response to the pulse signal. The counter value is associated with the detector signal. Related methods are also provided.

Techniques are disclosed for analog-to-digital conversion systems and methods with pulse generators. In one example, an imaging system includes an analog-to-digital converter (ADC). The ADC includes a comparator configured to generate a comparator output signal based on a first signal and a second signal. The comparator output signal is associated with a first state or a second state. The ADC further includes a pulse generator coupled to the comparator. The pulse generator is configured to generate a pulse signal in response to a transition of the comparator output signal from the first state to the second state. The ADC further includes a memory device coupled to the pulse generator. The memory device is configured to capture a counter value from a counter circuit in response to the pulse signal. The counter value is associated with the detector signal. Related methods are also provided.