A photoelectric conversion device includes: pixels forming columns and each configured to output a pixel signal; and comparator units provided to respective columns and each configured to receive the pixel signal from the pixels on a corresponding column and the reference signal. Each comparator unit includes a comparator having a first input node that receives the pixel signal and a second input node that receives the reference signal, a first capacitor that connects a reference signal line and the second input node, a second capacitor whose one electrode is connected to the second input node, and a select unit that connects the other electrode of the second capacitor to either the reference signal line or a reference voltage line. The other electrode of the second capacitor is connected to the reference signal line during first mode AD conversion and connected to the reference voltage line during second mode AD conversion.

An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

A plurality of comparison circuits each including a first terminal for inputting a first analog signal and a second analog signal and a second terminal connected to a wiring for transmission of a ramp signal A first operation changes an electric potential of the wiring from a predetermined electric potential to a first electric potential to cause at least one of the plurality of comparison circuits to retain a first offset. A second operation, after the first operation, converts the first analog signal into a digital signal. A third operation, after the second operation, changes the electric potential of the wiring to an electric potential included in a range of from the predetermined electric potential to the first electric potential. A fourth operation, after the third operation, converts the second analog signal into a digital signal.

A plurality of comparison circuits each including a first terminal for inputting a first analog signal and a second analog signal and a second terminal connected to a wiring for transmission of a ramp signal A first operation changes an electric potential of the wiring from a predetermined electric potential to a first electric potential to cause at least one of the plurality of comparison circuits to retain a first offset. A second operation, after the first operation, converts the first analog signal into a digital signal. A third operation, after the second operation, changes the electric potential of the wiring to an electric potential included in a range of from the predetermined electric potential to the first electric potential. A fourth operation, after the third operation, converts the second analog signal into a digital signal.

A ramp voltage generator includes: a ramping cell array including a plurality of ramping current cells; a calibration cell array including a plurality of calibration current cells; and a current-voltage converter suitable for converting a current supplied from activated ramping current cells among the ramping current cells and activated calibration current cells among the calibration current cells into a voltage to generate a ramp voltage.

A ramp voltage generator includes: a ramping cell array including a plurality of ramping current cells; a calibration cell array including a plurality of calibration current cells; and a current-voltage converter suitable for converting a current supplied from activated ramping current cells among the ramping current cells and activated calibration current cells among the calibration current cells into a voltage to generate a ramp voltage.

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

An imaging device includes a pixel array, a first converter, a second converter, a first ramp signal generation circuit that is disposed closer to the first converter than to the second converter and supplies a first ramp signal to the first converter and the second converter, a first connection line having one end connected to an output terminal of the first ramp signal generation circuit and including a portion extending away from an input terminal of the first converter in a path from the one end to the other end of the first connection line, and a second connection line having one end connected to the other end of the first connection line and the other end connected to the input terminal and including a portion extending closer to the input terminal in a path from the one end to the other end of the second connection line.