A successive approximation ADC includes: a comparator generating a judge signal related to an input analog and a reference signals; a SAR successively generating a register signal including a first and a second bit signals based on the judge signal and generating an AD conversion value of the input analog signal; a thermometer decoder switching different thermometer code conversion rules and converting the first bit signal to thermometer codes corresponding to the different thermometer code conversion rules in one AD conversion cycle; a first and a second DA converters respectively converting the thermometer codes to a first analog signal and the second bit signal to a second analog signal; an average value calculator averaging the AD conversion values by the thermometer codes. Two of the different thermometer codes have values that a high-order bit and a low-order bit groups by dividing total bits of the thermometer code equally are exchanged.

A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

A current regulator and a method for regulating a current flowing through a device such as a semiconductor light source is presented. The current regulator has a voltage controller coupled to a current steering circuit. The voltage controller is adapted to operate the current steering circuit in a linear mode.

A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

A digital-to-analog converter (DAC) system preferably includes one or more optical modulators and can optionally include one or more electronic DAC arrays. A method for digital-to analog conversion preferably includes receiving digital inputs and providing analog optical outputs. The method for digital-to analog conversion is preferably performed using the DAC system.

A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.

An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.

Methods of performing mixed-signal current-mode multiply-accumulate (MAC) operations for binarized neural networks in an integrated circuit are described in this disclosure. While digital machine learning circuits are fast, scalable, and programmable, they typically require bleeding-edge deep sub-micron manufacturing, consume high currents, and they reside in the cloud, which can exhibit long latency, and not meet private and safety requirements of some applications. Digital machine learning circuits also tend to be pricy given that machine learning digital chips typically require expensive tooling and wafer fabrication associated with advanced bleeding-edge deep sub-micron semiconductor manufacturing. This disclosure utilizes mixed-signal current mode signal processing for machine learning binarized neural networks (BNN), including Compute-In-Memory (CIM), which can enable on-or-near-device machine learning and or on sensor machine learning chips to operate more privately, more securely, with low power and low latency, asynchronously, and be manufacturable on non-advanced standard sub-micron fabrication (with node portability), that are more mature and rugged with lower costs. An example of enabling features of this disclosure is as follows: to save power in an always-on setting, reduce chip costs, process signals asynchronously, and reduce dynamic power consumption. Current mode signal processing is utilized in combination with CIM (to further reduce dynamic power consumption associated with read/write cycles in and out of memory) for bitwise counting of plurality of logic state 1 of plurality of XOR outputs for MAC arithmetic in BNNs.