Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

A neurostimulator incorporating a novel chip design that uses the principle of redundant signal crossfiring to overcome electronic component mismatch error in general and transistor mismatch error in particular, to yield superior quality neurostimulation signal generation, useful in enhancing the bidirectional human-machine interface in prosthesis operation for the restoration of somatosensation for an amputee.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

A method for determining an inverse impulse response of a communication channel by means of a PAM receiver comprises the following method steps: switching on the PAM receiver; if a second PAM transceiver is switched on, setting a difference between a clock frequency of the data signal and a sampling frequency of the first PAM transceiver; comparing a symbol that is output by the interpreter with a state that is supplied to the interpreter, and outputting an error value, wherein in each case a symbol associated with a sampling clock is compared with a state associated with the same sampling clock; adapting m filter coefficients of the equalizer to minimize error values; repeating the third method step and the fourth method step until an error limit value is reached.

A method for calibrating currents includes performing a first sorting operation on a plurality of first current sources according to current levels generated by the first current sources, performing a second sorting operation on a plurality of second current sources according to current levels generated by the second current sources, determining a first switching sequence for the first plurality of current sources according to a result of the first sorting operation, and determining a second switching sequence for the second plurality of current sources according to a result of the second sorting operation and the first switching sequence. The plurality of first current sources have a same target current value, and the plurality of second current sources have a same target current value.

Provided is a DA converter for outputting an analog signal according to an input digital signal, including a plurality of current output units to be input with the digital signal, which output a current according to the digital signal to a corresponding wiring, a conversion unit provided with a plurality of feedback paths respectively coupled to wirings corresponding to the current output units, and which selects at least one wiring among the wirings corresponding to the current output units and output an analog signal according to a current flowing in the selected wiring, and a first noise reduction unit provided with a plurality of first switches each of which switches whether to electrically connect to at least one wiring among the wirings corresponding to the current output units, and reduces a noise component generated in at least one of the plurality of current output units from the electrically coupled wiring.

An inductive current digital-to-analog converter (DAC) includes: a power supply input adapted to be coupled to a power supply; a load terminal adapted to be coupled to a load; an inductor between the power supply input and the load terminal; and inductor current control circuitry. The inductor current control circuitry has: a sense signal input configured to receive a sense signal representative of the inductor current; a control code input configured to receive a control code; a set of switches having respective control terminals; and a set of control circuit outputs coupled to the respective control terminals of the set of switches. The inductor current control circuitry is configured to adjust control signals provided to the set of control circuit outputs based on the sense signal and the control code.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

Numerous embodiments of a hybrid memory system are disclosed. The hybrid memory can store weight data in an array in analog form when used in an analog neural memory system or in digital form when used in a digital neural memory system. Input circuitry and output circuitry are capable of supporting both forms of weight data.

In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.