The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

A semiconductor circuit includes first and second DA converters which selects first and second reference voltages in response to upper m bits of input digital data, a select circuitry which outputs first to N-th selected input voltages in response to lower n bits of the input digital data; first to N-th differential input stages, an output stage and a first tail current source. Each of the first to N-th differential input stages includes a transistor pair. The i-th selected input voltage is supplied to the gates of a first MISFET of the i-th differential input stage and the gates of the second MISFETs of the first to N-th differential input stages are connected to the output node. The first tail current source controls the current levels of the first tail current in the first to N-th differential input stages in response to lower n bits of the input digital data.

A digital-to-analog convertor for a driving module of a display device is disclosed. The digital-to-analog convertor includes a plurality of switches, forming a tree structure with a plurality of stages for outputting one of a plurality of gamma voltages to an output end according to a plurality of bits of a digital input signal; and a bypass unit, coupled between a first output end of a first switch in the plurality of switches and the output end for adjusting a connection between the first output end and the output end according to a most significant bit in among the plurality of bits and the bits between the most significant bit and a first bit controlling the first switch in among the plurality of bits.

A digital-to-analog convertor for a driving module of a display device is disclosed. The digital-to-analog convertor includes a plurality of switches, forming a tree structure with a plurality of stages for outputting one of a plurality of gamma voltages to an output end according to a plurality of bits of a digital input signal; and a bypass unit, coupled between a first output end of a first switch in the plurality of switches and the output end for adjusting a connection between the first output end and the output end according to a most significant bit in among the plurality of bits and the bits between the most significant bit and a first bit controlling the first switch in among the plurality of bits.

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

An analog-to-digital circuit that digitizes an analog voltage. The analog-to-digital circuit includes plural comparators functionally connected to form a tree that has levels i, and each level i has branches j, and an encoder connected to the plural comparators and configured to generate a digitized value of an input analog voltage. Each comparator from a level i has first and second outputs, and each of the first and second outputs is electrically connected to an input of different comparators from a next level i+1 of the tree.