A measuring system for detecting switching states including a signal converter having signal inputs to each of which an associated binary switching signal representing a switching state can be applied. Electrical resistors, at which an associated measurement signal can be tapped on the basis of the associated binary switching signal, is connected downstream of each of the signal inputs, wherein the electrical resistors have resistance values, which differ from each other, and wherein the electrical resistors are connected in parallel to each other. The signal converter also has a signal output, which is connected downstream of the electrical resistors in order to provide a sum measurement signal at the signal output with a sum current strength, which sum measurement signal is formed from the sum of the measurement signals, and wherein the sum measurement signal has a current strength which can be uniquely assigned to a current strength reference value.

Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one releationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50Ω.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.

A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.