A digitally compensated hysteretic power supply with enhanced resolution is provided. Such a power supply includes a comparator that is used to compare a load current sense signal with an internal signal generated from a digital-to-analog converter (DAC). A compensation circuit at a DAC input operates to improve current accuracy beyond the given DAC resolution. The current sense signal is converted to its digital equivalent, which is fed to a proportional-integral (PI) compensation loop, which in turn generates a relatively precise high resolution DAC input value. The DAC uses the higher part of the DAC value. The lower part of the DAC value is treated as a duty cycle number, and the DAC output is toggled between two levels at this duty cycle. This toggling generates a current output signal having a value that is the average of the two toggled values.

Systems, devices, and methods for a high-voltage conversion circuit system comprising: an error detection and correction module configured to receive an analog input signal and a feedback signal and generate a correction signal; and an analog to pulse width modulation (PWM) module configured to receive the analog input signal and correction signal and generate a PWM output signal; where the generated PWM output signal is fed back to the error detection and correction module as said feedback signal.

A circuit for generation of a reference voltage for an electronic system, which circuit comprises at least one digital buffer (U21, U31, U32, U41, U51), a low pass filter (R21, C21; R31, C31; R41, C41; R51, C51) and an operational amplifier (OA21, OA31, OA41, OA51)), which circuit is adapted to revive an input in the form of a bandgap reference voltage into the digital buffer, which digital buffer is adapted to receive a digital input from a Pulse Width Modulated (PWM) signal, which digital buffer is adapted to generate an output signal adapted to be fed to the low pass filter, which output signal after filtration is adapted to be fed to a positive input terminal of the operational amplifier, which operational amplifier comprises a feedback circuit, which feedback circuit comprises at least one capacitor (C22, C32, C44, C54) adapted to be connected from an output terminal of the operational amplifier towards a negative input terminal of the operational amplifier so as to form an integrator, wherein the feedback circuit further comprises at least one chopped signal path (R22, S21; R33, R34, S32; R33, R35, C35, S31), which chopped signal is adapted to be modulated by the output signal of the digital buffer.

In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

Systems and methods for digital signal synthesis with variable sample rate digital-to-analog converters (DACs) in accordance with embodiments of the invention are described. One embodiment includes a digital frequency generator that includes a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; a frequency control word (FCW); where the DAC is sampled by the variable frequency sample clock; where the DDFS is clocked by the variable frequency sample clock; where the frequency/phase estimation circuit receives a the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; where the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, where the FCW is continuously adjusted to track the variable frequency sample clock.

Apparatus, systems, and methods for systems and methods for data signal multiplexing may be provided. According to an aspect a method for data signal multiplexing may be provided. The method includes interleaving, by a first 4-to-1 (4:1) multiplexer (MUX), a first set of four analog signals received from a first group of 4 Digital-to-Analog Converters (DACs) to generate a first interleaved analog output. The method may further include interleaving, by a second 4:1 MUX, a second set of four analog signals received from a second group of 4 DACs to generate a second interleaved analog output. Each of the first and the second interleaved analog output may be based on a first 8-unit interval (UI) window including four consecutive 2 UI windows. The method may further include interleaving, by a 2:1 MUX, the first interleaved analog output and the second interleaved analog output to generate a combined interleaved analog output.

A pulse density modulator encodes an electrical parameter of an external element into a data stream signal. The electrical parameter has a property which causes a predetermined error in the data stream signal. The pulse density modulator includes a digital to analog converter having a sensor element connectable to the external element, and an adjuster circuit adapted to adjust an output of the digital to analog converter based on the data stream signal to correct the predetermined error in the data stream signal. A corresponding method of correcting a data stream signal of a pulse density modulator is also presented.

A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

A digital-to-time converter circuit includes a scrambling and noise shaping circuit, a digital-to-analog converter (DAC), and a buffer circuit. The scrambling and noise shaping circuit includes an input and an output. The input is coupled to a delay input terminal. The scrambling and noise shaping circuit is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. The DAC includes an input and an output. The input of the DAC is coupled to the output of the scrambling and noise shaping circuit. The DAC is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. The buffer circuit includes an input and an output. The input of the buffer circuit is coupled to the output of the DAC. The output of the buffer circuit is coupled to a signal output terminal.