An analog to digital converter has an input, a plurality of quantizers, a plurality of feedback loops, and a plurality of filters. The input is configured to receive an input signal. The plurality of quantizers has the Nth quantizer, and the Nth quantizer has the Nth quantizer input and the Nth quantizer output. The Nth quantizer input is connected to the input. The plurality of feedback loops has the Nth feedback loop, and the Nth feedback loop is formed around the Nth quantizer output and the Nth quantizer input and configured to reduce the difference between the signal of the Nth quantizer output and an Nth reference signal at an Nth frequency region. The plurality of filters has an Nth filter. The Nth filter is configured to select the Nth frequency region. The feedback loops provide a way to control the effect of some nonidealities such as comparator offsets.

A system and method of digital to analog conversion including modulating a digital value D.sub.N-K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which D.sub.N-K comprises N-K least significant bits of an N-bit digital input value D.sub.N and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding D.sub.M to a value D.sub.K to provide a select value D.sub.KM in which D.sub.K includes the K remaining most significant bits of D.sub.N, and applying mismatch shaping of a total of at least P=2.sup.K elements of a P-element DAC per cycle based on D.sub.KM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.

A system and method of digital to analog conversion including modulating a digital value D.sub.NK with an oversampling delta sigma modulator to provide an M-bit coarse quantized value D.sub.M, in which D.sub.NK comprises NK least significant bits of an N-bit digital input value D.sub.N and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding D.sub.M to a value D.sub.K to provide a select value D.sub.KM in which D.sub.K includes the K remaining most significant bits of D.sub.N, and applying mismatch shaping of a total of at least P=2.sup.K elements of a P-element DAC per cycle based on D.sub.KM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.

A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.