Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

An A/D converter includes: an integrator circuit executing modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a modulation mode and a cyclic mode.

The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.

A dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator is disclosed. Radio frequency (RF) devices incorporating aspects of the present disclosure may support multiple wireless modes operating at different frequencies. Therefore, the RF devices have need for an ADC which is flexible and optimizable in terms of resolution, bandwidth, and power consumption. In this regard, the RF devices incorporate circuits, such as ADC circuits, which incorporate a discrete-time passive delta-sigma modulator. In order to improve the resolution of the delta-sigma modulator, a coarse ADC is deployed as a zooming unit to a single-bit passive delta-sigma modulator to provide a coarse digital conversion. Coarse conversion is used to dynamically update reference voltages at an input of the delta-sigma modulator using a multi-bit feedback digital to analog converter (DAC). The dynamic-zoom ADC supports multiple modes with improved power and quantization noise.

A pipeline ADC architecture with suitable feedback can implement noise shaping. By feeding back the residue generated by the last residue generating stage to selected locations in the pipeline ADC, the delays in a pipeline ADC can create a finite impulse response (FIR) filtered version of the quantization error. The FIR filtered quantization error is added to the signal and evaluated by the pipeline ADC, which results in spectral shaping of the quantization noise. Unlike a conventional pipeline ADC, the output of the backend stage is scaled and filtered by a noise transfer function (NTF) of the residue generating stages prior to combining the output with other outputs of the pipeline ADC. The processing of the shaped quantization noise by the backend stage results in further noise suppression.

Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

Provided are an analog-to-digital (AD) converter, a sensor processing circuit, and a sensor system capable of improving responsiveness of feedback control. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to sensor before first output part outputs the first digital data.