Data converter circuits and methods of operating the data converter circuits are disclosed. In some embodiments, a data converter circuit includes a charge measurement circuit. In some embodiments, the charge measurement circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data converter circuit includes the CTIA, a quantizer, a digital-to-analog converter, a summer, and a digital filter. In some embodiments, the data converter circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiment, a method includes integrating an input signal with a CTIA, determining whether a CTIA output signal is greater than a threshold, and reducing the CTIA output signal or forgoing the reducing based on the determination of whether the CTIA output signal is greater than the threshold.

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

A dynamic-zoom analog to digital converter (ADC) having a coarse flash ADC and a fine passive single-bit modulator is disclosed. Radio frequency (RF) devices incorporating aspects of the present disclosure may support multiple wireless modes operating at different frequencies. Therefore, the RF devices have need for an ADC which is flexible and optimizable in terms of resolution, bandwidth, and power consumption. In this regard, the RF devices incorporate circuits, such as ADC circuits, which incorporate a discrete-time passive delta-sigma modulator. In order to improve the resolution of the delta-sigma modulator, a coarse ADC is deployed as a zooming unit to a single-bit passive delta-sigma modulator to provide a coarse digital conversion. Coarse conversion is used to dynamically update reference voltages at an input of the delta-sigma modulator using a multi-bit feedback digital to analog converter (DAC). The dynamic-zoom ADC supports multiple modes with improved power and quantization noise.

An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

An A/D converter includes an analog input terminal, a successive approximation A/D converter connected to the analog input terminal, the successive approximation A/D converter for generating an upper conversion result at an upper conversion result terminal, the successive approximation A/D converter having an internal D/A converter generating an internal reference voltage at an internal reference voltage terminal, and a delta-sigma A/D converter connected to the analog input terminal and the internal reference voltage terminal, the delta-sigma A/D converter for generating a lower conversion result at a lower conversion result terminal.