A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.

The disclosure is directed to a system, device and method for data storage on implantable magnetizable fabric. The system includes implantable magnetizable fabric coupled to a graft segment of a prosthesis for being delivered into a body of a subject. The system includes information written on the implantable magnetizable fabric. The system further includes a magnetic detection device capable of, after the prosthesis is delivered into the body of the subject, detecting the implantable magnetizable fabric and accessing at least a portion of the information.

A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.

Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.

A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

A transmission device includes an encoding circuit and a modulation circuit. The encoding circuit is configured to encode first and second data stream portions of a transmission data stream in accordance with first and second encoding protocols, respectively, convert each M bit of the encoded second data stream portion into a high-resolution value of N bit, and generate a baseband data stream including the encoded first data stream portion and the converted second data stream portion. The modulation circuit is configured to perform a 2.sup.N-level pulse amplitude modulation with respect to each N bit of the encoded first data stream portion in the baseband data stream and each N bit of the converted second data stream portion in the baseband data stream, to generate a transmission signal. M is an integer equal to or greater than 1 and N is an integer greater than M.

This application relates to a codeword synchronization method, a chip, a network device, and a system. The codeword synchronization method includes: receiving a first data sequence, where the first data sequence includes a plurality of bits, and a codeword in the first data sequence includes extension information for verifying the codeword; selecting at least one group of bits from the plurality of bits as the extension information to perform verification, and determining a candidate bit in the plurality of bits based on a result of the verification; and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of the codeword that is in the first data sequence.

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.