Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.

Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.

A system includes an analog-to-digital converter (ADC) and a digital modulator coupled to the ADC, wherein the digital modulator comprises an output for providing a digital signal, wherein the digital modulator comprises a main signal path and a feedback path, and wherein the feedback path comprises a first digital gain stage having a first adjustable gain range.

A MEMS microphone module includes a MEMS microphone, a modulator connected downstream of the MEMS microphone, and an interference compensation circuit to apply an interference compensation signal to an input of the modulator, the interference compensation signal being opposed to a low-frequency signal interference present at the input of the modulator or a block connected upstream of the input of the modulator.

A device includes a sensor configured to output an analog sensor signal, an analog-to-digital converter circuit configured to convert the analog sensor signal into a sigma-delta-modulated digital signal having a bit width of n bits, and a pulse width modulator configured to generate a pulse-width-modulated signal based on the sigma-delta-modulated digital signal.

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that make it possible to cope with an output of a PCM signal using one DSD signal. A distribution apparatus includes an extraction section that, in a case where a PCM signal having a predetermined sampling frequency is generated from a DSD signal, extracts a predetermined number of samples from the DSD signal around samples at a predetermined interval determined by the predetermined sampling frequency, and a filtering section that generates the PCM signal having the predetermined sampling frequency by filtering the extracted predetermined number of samples. The present technology is applicable to, for example, a distribution apparatus, etc., that distributes the PCM signal to a client apparatus.

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that permit switching between a plurality of DSD signals having different sampling frequencies using a simple configuration. An acquisition section acquires a digital audio signal having a given sampling frequency selected from among the plurality of digital audio signals acquired by delta-sigma modulating an audio signal at a plurality of sampling frequencies. An interpolation section subjects the acquired digital audio signal to a pre-interpolation process when the sampling frequency of the acquired digital audio signal is lower than an operating clock of a delta-sigma demodulator. The present technology is applicable, for example, to a signal processing apparatus.