A quantizer and a method for a sigma-delta modulator circuit that may be used as a component within an adaptive-noise cancelling headphone are presented. An apparatus includes a quantizer to receive an input signal with successive input values and quantizes the input signal at discrete intervals. This is done by mapping the input value of the input signal at each interval to one of a plurality of quantization levels with three or more quantization levels that are non-uniformly spaced. The plurality of quantization levels has a first portion with two or more quantization levels having the same sign and being proportional to a first fraction having one as its numerator and two to a power of a first variable as its denominator, the first variable being an integer and having a different value for each of the two or more quantization levels of the first portion.

A digital microphone device includes circuitry that can reduce the risk of noise caused due to an idle tone frequency component in a digital signal output by the digital microphone device. In stereo mode and other applications where interference occurs between two or more such microphones, each microphone device includes a digital output having a corresponding idle tone frequency, one of which is offset to shift noise components outside of a desired frequency range.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

The present technology relates to a signal processing apparatus, a signal processing method, and a program that make it possible to cope with an output of a PCM signal using one DSD signal. A distribution apparatus includes an extraction section that, in a case where a PCM signal having a predetermined sampling frequency is generated from a DSD signal, extracts a predetermined number of samples from the DSD signal around samples at a predetermined interval determined by the predetermined sampling frequency, and a filtering section that generates the PCM signal having the predetermined sampling frequency by filtering the extracted predetermined number of samples. The present technology is applicable to, for example, a distribution apparatus, etc., that distributes the PCM signal to a client apparatus.

A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

A digital microphone device includes circuitry that can reduce the risk of noise caused due to an idle tone frequency component in a digital signal output by the digital microphone device. In stereo mode and other applications where interference occurs between two or more such microphones, each microphone device includes a digital output having a corresponding idle tone frequency, one of which is offset to shift noise components outside of a desired frequency range.

A digital microphone device includes circuitry that can reduce the risk of noise caused due to an idle tone frequency component in a digital signal output by the digital microphone device. In stereo mode and other applications where interference occurs between two or more such microphones, each microphone device includes a digital output having a corresponding idle tone frequency, one of which is offset to shift noise components outside of a desired frequency range.

A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

A MEMS microphone module includes a MEMS microphone, a modulator connected downstream of the MEMS microphone, and an interference compensation circuit to apply an interference compensation signal to an input of the modulator, the interference compensation signal being opposed to a low-frequency signal interference present at the input of the modulator or a block connected upstream of the input of the modulator.