H03M7/6017

ADAPTIVE ARITHMETIC CODING OF AUDIO CONTENT

Disclosed is a system and computer program product of encoding audio content and corresponding method. The method includes determining a characteristic of the audio content, the characteristic of the audio content including at least one of a type or a property of the audio content. Also the method includes classifying the audio content based on the characteristic of the audio content and determining probabilities for multiple predefined audio coding symbols associated with the audio content by calculating a probability for each of the audio coding symbols based on the result of the classification, the probability for an audio coding symbol indicating a frequency at which the audio coding symbol occurs in the audio content. Further, the method encoded the audio content based on the audio coding symbols and the corresponding probabilities to obtain a code value, the code value representing a compression coding format of the audio content.

Hybrid software-hardware implementation of lossless data compression and decompression
09923577 · 2018-03-20 · ·

A system, method and product for providing data compression and decompression. A method is disclosed that includes: utilizing a CPU to perform a matching-bytes search, byte-oriented search result coding, and content analysis on a set of raw data to generate a set of initially compressed data; forwarding the set of initially compressed data from the CPU to a hardware accelerator; utilizing the hardware accelerator to perform search result re-coding, table construction, and encoding to generate a set of further compressed data; and forwarding the set of further compressed data back to the CPU.

Technologies for efficient LZ77-based data decompression

Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

HYBRID SOFTWARE-HARDWARE IMPLEMENTATION OF LOSSLESS DATA COMPRESSION AND DECOMPRESSION
20180069568 · 2018-03-08 ·

A system, method and product for providing data compression and decompression. A method is disclosed that includes: utilizing a CPU to perform a matching-bytes search, byte-oriented search result coding, and content analysis on a set of raw data to generate a set of initially compressed data; forwarding the set of initially compressed data from the CPU to a hardware accelerator; utilizing the hardware accelerator to perform search result re-coding, table construction, and encoding to generate a set of further compressed data; and forwarding the set of further compressed data back to the CPU.

Methods for accelerating hash-based compression and apparatuses using the same

The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.

High-throughput compression of data

A mechanism is provided for high-throughput compression of data. Responsive to receiving an indication of a match of a current 4-byte sequence from an incoming data stream to stored hash values in a set of hash tables, numerous variables are set to initial values. Responsive to receiving a subsequent 4-byte sequence from the incoming data stream and determining that an active match variable is set to one, the subsequent 4-byte sequence is compared to data in a copy of the incoming data stream in memory at an active position with a predefined length offset. A constraint variable is set to a number of bytes for which the match is to be extended. Responsive to the constraint variable being below a predetermined number, a length, distance pair is output indicating a match to a previous pattern in the incoming data stream.

Predicate application through partial compression dictionary match

Methods and apparatus, including computer program products, implementing and using techniques for predicate application using partial compression dictionary match. A search strategy is developed for each predicate to be applied to compressed data. The compressed data is searched using the search strategy to locate the compression symbols identified in the search strategy. In response to locating a compression symbol from the search strategy in the compressed data, a respective row and applying the predicate is decompressed and a respective row that matches the predicate is returned to a database engine or an application.

HYBRID COMPRESSION FOR LARGE HISTORY COMPRESSORS
20170192709 · 2017-07-06 ·

A compression engine and method for optimizing the high compression of a content addressable memory (CAM) and the efficiency of a static random access memory (SRAM) by synchronizing a CAM with a relatively small near history buffer and an SRAM with a larger far history buffer. An input stream is processed in parallel through the near history and far history components and an encoder selects for the compressed output the longest matching strings from matching strings provided by each of the near history and far history components. A further optimization is enabled by selectively disabling one or the other of the two types of compressors.

Hardware apparatuses and methods for data decompression

Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

Runtime reconfigurable compression format conversion with bit-plane granularity

A runtime bit-plane data-format optimizer for a processing element includes a sparsity-detector and a compression-converter. The sparsity-detector selects a bit-plane compression-conversion format during a runtime of the processing element using a performance model that is based on a first sparsity pattern of first bit-plane data stored in a memory exterior to the processing element and a second sparsity pattern of second bit-plane data that is to be stored in a memory within the processing element. The second sparsity pattern is based on a runtime configuration of the processing element. The first bit-plane data is stored using a first bit-plane compression format and the bit-plane second data is to be stored using a second bit-plane compression format. The compression-conversion circuit converts the first bit-plane compression format of the first data to be the second bit-plane compression format of the second data.