HYBRID COMPRESSION FOR LARGE HISTORY COMPRESSORS

Abstract

A compression engine and method for optimizing the high compression of a content addressable memory (CAM) and the efficiency of a static random access memory (SRAM) by synchronizing a CAM with a relatively small near history buffer and an SRAM with a larger far history buffer. An input stream is processed in parallel through the near history and far history components and an encoder selects for the compressed output the longest matching strings from matching strings provided by each of the near history and far history components. A further optimization is enabled by selectively disabling one or the other of the two types of compressors.

Claims

1. A compression engine for large history compressors, comprising: a near history component implemented in a first type of compressor; a far history component implemented in a second type of compressor; wherein matching in the near history is synchronized with matching in the far history to generate a compressed output and wherein either the first type of compressor or the second type of compressor is selectively disabled then powered off for some input strings or for some engine conditions.

2. A compression engine as in claim 1, wherein the first type of compressor is implemented in content addressable memory (CAM) and the second type of compressor is implemented in static random access memory (SRAM).

3. A compression engine as in claim 1, wherein a condition is engine power consumption exceeding some preset threshold.

4. A compression engine as in claim 1, wherein a condition is when one type compressor is substantially producing better results than the other type compressor.

5. A compression engine as in claim 4, wherein the second type compressor is partially disabled by selectively turning off some SRAM banks or some SRAM entries.

6. A compression engine as in claim 1, wherein the far history component further comprises: a far history buffer for storing an input string at a next buffer address; a hash table for storing said next buffer address at a hash of a token of said input string.

7. A compression engine as in claim 6, wherein the hash table contains a set of entries for each hash value.

8. A compression engine as in claim 7, wherein a token for a current input is matched to a prior location in the far history buffer.

9. A compression engine as in claim 8, wherein the match of the token is extended to include a next input.

10. A compression engine as in claim 9, wherein a longest matching string is sent to the encoder when the match cannot be extended to a next input.

11. A compression method for large history compressors, comprising: processing an input stream in parallel through a near history component and a far history component, the near history component being implemented in a first type of compressor and the far history component being implemented in a second type of compressor; synchronizing matching by the near history component with matching by the far history component; and generating a compressed output from the synchronized matching, wherein either the first type of compressor or the second type of compressor is selectively disabled then powered off for some input strings or for some engine conditions.

12. A compression method as in claim 11, wherein the first type of compressor is implemented in content addressable memory (CAM) and the second type of compressor is implemented in static random access memory (SRAM).

13. A compression engine as in claim 11, wherein a condition is engine power consumption exceeding some preset threshold.

14. A compression method as in claim 11, wherein a condition is when one type compressor is substantially producing better results than the other type compressor.

15. A compression method as in claim 14, wherein the second type compressor is partially disabled by selectively turning off some SRAM banks or some SRAM entries.

16. A compression method as in claim 13, further comprising: storing an input string at a next buffer address in a far history buffer; and storing said next buffer address at a hash of a token of said input string.

17. A compression method as in claim 16, wherein the hash table contains a set of entries for each hash value.

18. A compression method as in claim 17, further comprising matching a token for a current input to a prior location in the far history buffer.

19. A compression method as in claim 18, further comprising extending the match of the token to include a next input.

20. A compression method as in claim 19, wherein a longest matching string is sent to an encoder when the match cannot be extended to a next input.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

[0019] FIG. 1 is a chart showing compression efficiency as a function of history buffer sizes of a compression algorithm called Embedded Lossless Data Compression (ELDC) algorithm commonly used in tape data storage systems.

[0020] FIG. 2 is a schematic diagram showing coordination between the 1 K CAM and the 16 K dictionary.

[0021] FIG. 3 is a schematic showing how the input stream of bytes is allocated over the CAM and hash based dictionaries.

[0022] FIG. 4 shows a four-way hash table.

[0023] FIG. 5 is a schematic showing how the input stream is loaded into a four-way hash table.

[0024] FIGS. 6A and 6B are schematics showing coordination between the history buffer and a four-way hash table.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0025] Referring now to the drawings, and more particularly to FIG. 1, there is shown the data on compression as a function of history buffer size leading the inventors to develop the partitioning of memory requirements between a near history and a far history. Graph line 110 shows data compression using the ELDC algorithm as measured by the bits/char scale on the y-axis on the left side of the graph dependent upon history buffer size shown on the x-axis. A substantial compression from 8 bits/char (uncompressed) to less than 4 bits/char 115 is observed with a 1 K history buffer, with diminishing compression improvement approaching 3 bits/char as the history buffer size is increased up to 64 K. Graph line 120 shows the additional but diminishing compression improvement as a percentage of the compression achieved using a 1 K history buffer. The percentage is measured by the y-axis scale on the right side of the graph dependent upon history buffer size shown on the x-axis.

[0026] As shown in FIG. 2, the hybrid compression system includes a 1 KB CAM based dictionary 220 and a 16 KB SRAM based dictionary 230 both of which try to find repetitions in the input stream 205, and an encoder unit 240 that selects the longest string on the raw phrase 210 among many matching strings (221,231) discovered by both units, based on the offset (222,232) and length (223,233) in relation to the raw phrase 210. When the longest string selected by the encoder 240 is from the 1 KB CAM dictionary 220 the encoder 240 sends a reset signal to the 16 KB SRAM dictionary 230, and when the longest string is from the 16 KB SRAM dictionary 230 the encoder 240 sends a reset signal to the 1 KB CAM dictionary 220. The 1 KB CAM 220 retains the recent 1 KB history but it can discover the longest possible match within that history with 100% certainty. The 16 KB Hash based dictionary 230 retains much longer history, but with a small probability it can forget the location of the longest possible match within that 16 KB history.

[0027] Each reset signal (225,235) indicates to its respective dictionary (220,230) that the other dictionary has found a longer matching string (winner). Therefore, the losing dictionary may stop its matching procedure until the winning dictionary stops matching the input string, i.e. removal of the reset signal.

[0028] As shown in FIG. 3, input 305 is fed to the 1 KB CAM 320 and the 16 KB dictionary 330 in parallel. The 16 KB dictionary 330 tokenizes the input bytes in units of 3 or 4 bytes for a more selective dictionary lookup to eliminate too many short length matches, e.g. those that are shorter than 3 bytes. Token units of 3 bytes (e.g. token0 340 and token3 343) are shown in FIG. 3. However, other token sizes are possible without violating the spirit of the invention. The token is then used for searching the history buffer.

[0029] The CAM unit need not tokenize the input, as by design and definition a CAM can locate all 1 byte matches in its memory in a single cycle. The CAM unit will later eliminate those short length matches, by whittling down the list of matches as more input bytes arrive, finally resulting in a single longest matching string in the 1 KB history.

[0030] The SRAM based dictionary is comprised of an SRAM based hash table (HT) and an SRAM based history buffer. The hash table and its operation are shown in FIGS. 4 and 5. A hash table (HT) 400 is used to identify the history buffer location or locations of an input token 510 by using a hash function 520 to compute a hash value between zero and S1 in a hash table 400 with S entries. HT operates similar to a direct mapped or an N-way set associative computer cache memory. In a typical embodiment, N=2 or N=4 is feasible, however to those skilled in the art it will be obvious that other N values are possible without violating the spirit of the invention. With larger associativity values N, HT retains more repetitions of the same token. For example in the N=4 case, as shown in FIG. 4, a token may be matched to up to four separate locations in the history buffer, as each HT set (e.g. 410) can retain four pointers. Each HT set contains N entries and each HT entry contains a pointer to the history buffer, referred to as HB address (e.g. 420) in FIG. 4.

[0031] Similar to that of computer cache organizations the hash table implements a replacement policy which determines which entry to evict from an HT set when the set is full. For example, in the 4-way HT example of FIG. 4, when a new, 5th token maps to a full set, the Least Recently Used (LRU) policy will replace one of the least recently used entries in the set with the new token. Those skilled in the art may employ other replacement policies such as first in first out (FIFO) or random replacement, or other policies without violating the spirit of the invention.

[0032] As with computer cache memories, the size of the hash table (i.e. the number of sets S) as well as the associativity impacts the hash table hit rate. Larger HT reduces collisions of tokens, which happens when different tokens hash in to the same set. In practice, design simulations may be used to determine the hash table size.

[0033] As shown in FIG. 5, a token is hashed in to a log.sub.2 S bits of an HT address. The main purpose of the Hash function (HF) 520 is to provide a mapping from a token 510 to a set (e.g. 410) in the hash table. HF 520 is designed to ensure that the tokens are uniformly mapped across the entire hash table to maintain the expected hash table hit rate. Hash functions may be constructed by XOR'ing the token bits or using any other appropriate hashing function.

[0034] FIG. 6A shows how HT is looked up (read) and updated (write). Let's examine the update operation first. The next_addr register 650 increments in each cycle; it always points to the next free history buffer (HB) location to which new input is written; in the example of FIG. 6A, the input (0 1 2 3) 610 is written to location P 620. In the same cycle, the next_addr register 650 value P is also written to the HT entry 630 in the set 640 responsible for remembering the HT location computed by hash function HF 625 of the 3 byte input token (0 1 2) 615; in other words: HT [HF(012)]P. Now, the HT has a record of where the token (0 1 2) 615 has been seen in the 16 KB window.

[0035] Note that some of the tokens may span consecutive locations in HB, namely the locations P and P+1. Therefore, in one embodiment of the invention it may take two cycles to read HB. In another simplified embodiment in which two reads may not be possible, as a design tradeoff, matching of a token spanning consecutive locations will be forfeited and will result in a no history match.

[0036] Using FIG. 6B, we can examine the HT lookup. Suppose the token (0 1 2) 615 repeats later in the input stream 605. The hash function HF 625 hashes the token (0 1 2) 665 to the same HT location set 640 as the previous occurrence of itself. Then, from HT entry 630 the address P is read. Now we have the address P 620 as a hintwith a high probabilitywhere the previous occurrence of the token (0 1 2) may be found in HB.

[0037] Then, the location P 620 contents are read from HB. The read value is compared to the current input token 665 to determine if there is an actual match. If matched, then the pointer P is written in to a MATCH register M employed for tracking the location and length of matching strings. In an N-way organization, since up to N matches are possible, there will be N match registers M[0..N1] as well as N associated length registers to count match length of each. For example, in HT location set 640 there may be corresponding HB pointers in HT entries 630, 631, 632 and 633. The values in the HB corresponding to each of these pointers is read to determine if there is an actual match with token 655 in the same manner as with the value at location P 620, and if there is a match the pointer is written to the corresponding MATCH register M[0..3]. Regardless of its match status, the string 605 will be placed in the history buffer location 621 pointed to by the next address register 651, and this location 621 will be remembered with an entry in the HT set 640, displacing an existing entry if no open entries are available.

[0038] Once a match starts hash table lookups cease. Instead each new byte after the matched token 655 in the input stream 605 is compared to next byte in the history buffer location in the M register, i.e. HB[M+1]. If the match is continuing, it means that there exists a longer matching string in the history buffer, and therefore the M and Length registers are incremented. The process repeats for all HB pointers in HT location set 640 until input bytes stop matching the history buffer, at which time the dictionary unit sends the longest match address and length to the compression encoder according to FIG. 2. After matches stop, the hash table lookup operation resumes for the next set of input bytes.

[0039] One aspect of the invention is the selective disabling of first and second type compressors. Processor chips and I/O devices incorporating the compressors described by this invention are often subject to environmental and physical conditions such as power consumption. When the power consumption of the chip exceeds a certain threshold, or when the device battery is near empty, then one of the two types of compressors may be fully or partially shutdown without effecting the correctness of the operations however negligibly degrading the compression effectiveness. As stated before, it has been observed that most string matches occur in the near history. When a threshold condition is met, the far history compressor may be fully or partially shutdown. One condition is when power exceeds a high watermark. Another condition is when the near history compressor is substantially producing the string matches and the far history compressor is contributing very little to the results. Under this condition the far history compressor can be turned off to save energy even though the high watermark has not been exceeded. In the same manner, the far history compressor may be partially shutdown when only certain parts of the far history, for example the history less than 16 Kbytes (vs 32 KB required), are contributing substantially to the compression effort.

[0040] While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.