Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of , wherein is equal to raised to the (2.sup.m/41) power, is equal to a raised to the (2.sup.m/2+1) power, and is a primitive element of GF(2.sup.m). In another embodiment, the system receives a (N, N2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of , wherein is equal to raised to the (2.sup.m/41) power, is equal to a raised to the (2.sup.m/2+1) power, and is a primitive element of GF(2.sup.m). In another embodiment, the system receives a (N, N2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.

An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method and the frame stream, and constructs a picture coded signal.

A frame coding unit generates individual picture signal information from a moving picture signal, and outputs a frame code value which is a numeric value to be obtained as a result of coding picture signal information of each frame. A variable length coding unit decomposes the frame code value into unit frame code values which are basic units of coding, converts the unit frame code values into frame code words using only a single code table, and constructs a frame stream by combining the converted frame code words. A multiplexing unit multiplexes a header stream which is constructed through a method equivalent to a conventional method and the frame stream, and constructs a picture coded signal.

An audio transmitter processor for generating an error protected frame using encoded audio data of an audio frame, the encoded audio data for the audio frame having a first amount of information units and a second amount of information units, has: a frame builder for building a codeword frame having a codeword raster, wherein the frame builder is configured to determine a border between a first amount of information units and a second amount of information units so that a starting information unit of the second amount of information units coincides with a codeword border; and an error protection coder to obtain a plurality of processed codewords representing the error protected frame.

An audio transmitter processor for generating an error protected frame using encoded audio data of an audio frame, the encoded audio data for the audio frame having a first amount of information units and a second amount of information units, has: a frame builder for building a codeword frame having a codeword raster, wherein the frame builder is configured to determine a border between a first amount of information units and a second amount of information units so that a starting information unit of the second amount of information units coincides with a codeword border; and an error protection coder to obtain a plurality of processed codewords representing the error protected frame.

According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.

According to one embodiment, a decoding device that decodes a multi-dimensional error correction code having two or more component codes includes a storage unit that stores therein the multi-dimensional error correction code, an additional-information storage unit that manages each syndrome of the at least two component codes or a reliability flag indicating whether the syndrome has a value of 0 or other than 0, a decoder that performs a first decoding process in a unit of component code with respect to the multi-dimensional error correction code stored in the storage unit to detect an error vector of each component code, and a detection unit that determines whether detection of the error vector by the decoder is false detection, based on the syndrome or the reliability flag stored in the additional-information storage unit.