A data processing method, an apparatus, and a device are disclosed. The data processing method may be performed by a first communications device, and the first communications device is a transmit end of encoded data. The first communications device may send a high-order signal to a second communications device by using a plurality of parallel channels, and information bits in the parallel channels are arranged in a specified order. The method helps improve a transmission rate in a parallel channel transmission scenario, and helps the second communications device perform correct decoding.

Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The output RS blocks are then turbo coded. The size of the output RS blocks is selected to match the input of the turbo encoder. The bits from the RS blocks may be interleaved to create the input turbo blocks. Cyclic Redundancy Check (CRC) parity bits may be added to the data prior to RS coding.

The invention relates to a detection circuit, a detection method, an electronic device, and a computer-readable storage medium. The detection circuit includes: an error correction coding module configured to obtain data to be checked, and perform, based on an error correction coding logic, error correction coding on the data to be checked, to output target coded data; a data mask interface configured to receive comparison coded data, where the comparison coded data is associated with ideally coded data of the data to be checked; a comparison checking module configured to perform a checking comparison on the target coded data and the comparison coded data to output a checking comparison result; and a logic verification module configured to determine a coding verification result of the error correction coding module based on the checking comparison result. The comparison checking data verifies correctness of the error correction coding logic.

There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.

A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.