A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

The present disclosure relates to the field of communication technologies, and discloses a polar coding/decoding method and apparatus, to improve sequence lookup efficiency. The method includes: obtaining a first sequence from a polar code construction sequence table based on a coding parameter, where the polar code construction sequence table includes at least one coding parameter and at least one sequence corresponding to the at least one coding parameter, the at least one coding parameter is mapped to the at least one sequence in a one-to-one manner, the first sequence is one of the at least one sequence; selecting serial numbers of K polarized channels from the first sequence based on a rate matching scheme and/or a reliability order; placing to-be-coded bits based on the selected serial numbers of the K polarized channels; and performing polar coding, to obtain a coded bit sequence.

Devices for using a neural network to choose an optimal error correction algorithm are disclosed. An example device includes a decoding controller inputting at least one of the number of primary unsatisfied check nodes (UCNs), the number of UCNs respectively corresponding to at least one iteration, and the number of correction bits respectively corresponding to the at least one iteration to a trained artificial neural network, and selecting any one of a first error correction decoding algorithm and a second error correction decoding algorithm based on an output of the trained artificial neural network corresponding to the input, and an error correction decoder performing error correction decoding on a read vector using the selected error correction decoding algorithm. The output of the trained artificial neural network may include a first predicted value indicating a possibility that a first error correction decoding using the first error correction decoding algorithm is successful.

A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Disclosed are systems, methods, and software for generating spatially-coupled low-density parity-check (SC-LDPC) codes. A method for generating SC-LDPC codes includes generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, and also includes assigning at least one of the generated one or more QC-LDPC codes as one or more template codes. The method further includes copying at least a portion of the one or more template codes to introduce irregularity. The method also includes shifting one or more template codes on a sub-block basis to generate at least one SC-LDPC code. As compared to known LDPC code generation modalities, the disclosed invention provides a simplified technique for implementation in streamlined hardware which has more general applicability across both present, and anticipated, communication systems, including those adapted for use with optical communications, wireless communications, and 5G as well as future 6G.