In a transmission device, a signal processing circuit generates an aggregate physical layer convergence protocol data unit (A-PPDU) by adding a guard interval to each of a first part of a first physical layer convergence protocol data unit (PPDU) transmitted over each of a first through L′th channel of a predetermined channel bandwidth, where L is an integer of 2 or greater, a second part of the first PPDU transmitted over each of an (L+1)′th through P′th channel, which is a variable channel bandwidth that is N times the predetermined channel bandwidth, where N is an integer of 2 or greater and P is an integer of L+1 or greater, and a second PPDU transmitted over the (L+1)′th through P′th channel. A wireless circuit transmits the A-PPDU.

A transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed using a parity check matrix with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

Apparatuses for transmitting and receiving a signal in a communication system are provided. An apparatus of a receive device includes a receiver configured to receive, from a transmit device, a signal comprising remaining bits of parity bits after puncturing, wherein the parity bits are obtained by adding at least one shortened bit to information bits to obtain input bits for an encoding, if a number of the information bits is less than a number of the input bits for the encoding; and a hardware processor configured to determine a number of puncture bits for the parity bits, generate an output signal by adding at least one value corresponding to the number of the puncture bits to the signal, and decode the output signal.

Methods, systems, and apparatus are provided for encoding code blocks for transmission in a wireless communication system. An example encoding method in a wireless communication system includes determining, for one or more code blocks of a transport block, that at least one of a plurality of criteria is met, wherein the plurality of criteria includes that a coding rate (R) is less than or equal to ¼ or that a transport block size (TBS) is less than or equal to 3824 bits and the R is less than or equal to ⅔. The one or more code blocks are encoded using low-density parity-check (LDPC) base graph 2, wherein a maximum code block size is 3840 bits. The one or more encoded code blocks are transmitted over the wireless network.

A method for product decoding within a data storage system includes receiving data to be decoded within a first decoder; performing a plurality of decoding iterations to decode the data utilizing a first decoder and a second decoder; and outputting fully decoded data based on the performance of the plurality of decoding iterations. Each of the plurality of decoding iterations includes (i) decoding the data with the first decoder operating at a first decoder operational mode to generate once decoded data; (ii) sending the once decoded data from the first decoder to the second decoder; (iii) receiving error information from the first decoder with an artificial intelligence system; (iv) selecting a second decoder operational mode based at least in part on the error information that is received by the artificial intelligence system; and (v) decoding the once decoded data with the second decoder operating at the second decoder operational mode to generate twice decoded data; and outputting fully decoded data based on the performance of the plurality of decoding iterations.

Provided are a bit flipping device and method and a computer readable program for the same. The bit flipping device for input data having a two-dimensional array pattern includes: a clustering unit configured to generate at least one input data sequence based on the two-dimensional array pattern of the input data and classify the input data sequence into at least one cluster according to a preset method; and a bit flipping unit configured to perform bit flipping on erroneous bits in the input data sequence based on the classified cluster. Therefore, it is possible to further reduce inefficiency while further reducing system complexity compared to the existing error correction code-based bit flipping method by coupling the bit flipping device to an output side of a partial response maximum likelihood (PRML) detector to classify an output value of the PRML detector into at least one cluster and perform bit flipping based on the classified result.

The invention relates to a detection circuit, a detection method, an electronic device, and a computer-readable storage medium. The detection circuit includes: an error correction coding module configured to obtain data to be checked, and perform, based on an error correction coding logic, error correction coding on the data to be checked, to output target coded data; a data mask interface configured to receive comparison coded data, where the comparison coded data is associated with ideally coded data of the data to be checked; a comparison checking module configured to perform a checking comparison on the target coded data and the comparison coded data to output a checking comparison result; and a logic verification module configured to determine a coding verification result of the error correction coding module based on the checking comparison result. The comparison checking data verifies correctness of the error correction coding logic.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store a plurality of codewords in the memory device. Each codeword of the plurality of codewords includes host data and parity data corresponding to the host data. Less than all of the plurality of codewords further includes statistics corresponding to the host data. Each statistic of the plurality of codewords is the same or different as another statistic of the plurality of codewords. The statistics are either incremental statistics, adaptive statistics, or both incremental statistics and adaptive statistics.