Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

A system for a fiber-optic network includes a transceiver. The transceiver includes a fiber-optic interface unit and a host unit. The host unit includes a low-complexity error correction decoder and a high-complexity error correction decoder. One or both from the low-complexity error correction decoder and the high-complexity error correction decoder are selected to decode input data from the fiber-optic interface unit, the input data including codewords.

An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

A memory system comprising a qubit array configured to store therein one or more entangled qubit states encoded using a quantum stabilizer code. The memory system further comprises a quantum-state-refresh module configured to refresh an entangled qubit state in the qubit array when a degradation error is detected therein. The quantum-state-refresh module is further configured to detect the degradation error by performing a redundant measurement of a set of syndrome values corresponding to the quantum stabilizer code. The redundant measurement is based on an error-correction code defined using the generator matrix of the quantum stabilizer code and a corresponding supplemental parity-check matrix. In an example embodiment, each of the generator and supplemental parity-check matrices has a respective inclined-stripe form.

A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.