A magnetic tape device or system can store erasure encoded data that generates a multi-dimensional erasure code corresponding to an erasure encoded object comprising a code-word (CW). The multi-dimensional erasure code enables using a single magnetic tape in response to a random object/file request, and correct for an error within the single magnetic tape without using other tapes. Encoding logic can further utilize other magnetic tapes to generate additional parity tapes that recover data from an error of the single magnetic tape in response to the error satisfying a threshold severity for a reconstruction of the erasure coded object or chunk(s) of the CW. The encoding logic can be controlled, at least in part, by one or more iterative coding processes between multiple erasure code dimensions that are orthogonal to one another.

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.

A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

In a memory controller for performing error correction decoding, using an iterative decoding scheme, the memory controller includes a variable node update module for allocating the initial LLR values to variable nodes, and updating values of the variable nodes, using the initial LLR values and Check to Variable (C2V) messages corresponding to the variable nodes in an ith iteration, a syndrome checker for performing a syndrome check, using the values of the variable nodes updated in the ith iteration, and a reversal determiner for determining whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of C2V messages corresponding to the target variable node, when the syndrome check corresponding to the ith iteration fails.

A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.