An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.

The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.

In a memory controller for performing error correction decoding, using an iterative decoding scheme, the memory controller includes a variable node update module for allocating the initial LLR values to variable nodes, and updating values of the variable nodes, using the initial LLR values and Check to Variable (C2V) messages corresponding to the variable nodes in an ith iteration, a syndrome checker for performing a syndrome check, using the values of the variable nodes updated in the ith iteration, and a reversal determiner for determining whether to reverse the sign of an initial LLR value of a target variable node based on a ratio of signs of C2V messages corresponding to the target variable node, when the syndrome check corresponding to the ith iteration fails.

A hybrid type iterative decoding method for a three-dimensional turbo product code (TPC) having a first axis (FA), a second axis (SA), and a third axis (TA) including: a parallel decoding step of applying a predetermined decoding algorithm (PDA) in parallel to current FA and SA input values (IVs) which are determined based on at least two previous decoding values (DVs), respectively, among the previous FA, SA and TA DVs which are generated in advance to generate a current FA DV and a current SA DV, respectively; a serial decoding step of applying PDA to a current TA IV determined based on the current FA and SA DVs to generate a current TA DV; and performing hard decision based on the current FAs DV, the current SA DV, the current TA DV, and the received signal value.

A magnetic tape device or system can store erasure encoded data that generates a multi-dimensional erasure code corresponding to an erasure encoded object comprising a code-word (CW). The multi-dimensional erasure code enables using a single magnetic tape in response to a random object/file request, and correct for an error within the single magnetic tape without using other tapes. Encoding logic can further utilize other magnetic tapes to generate additional parity tapes that recover data from an error of the single magnetic tape in response to the error satisfying a threshold severity for a reconstruction of the erasure coded object or chunk(s) of the CW. The encoding logic can be controlled, at least in part, by one or more iterative coding processes between multiple erasure code dimensions that are orthogonal to one another.

A method of reading an optical code (20) is provided that has a plurality of code words, wherein image data having the optical code (20) are recorded and evaluated to read out the code words, and wherein it is determined by a test process whether the code is read correctly. In this respect, a code word at at least one position of the code (20) is replaced with a code word known for this position in a pre-correction and the test process is carried out after the pre-correction.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Disclosed is a three-dimensional TPC decoding apparatus. A three-dimensional TPC decoding apparatus includes an X decoder which decodes an X axis of an m-th upper half layer based on decoding results of a Y axis and a Z axis of an m1-th upper half layer; a Y decoder which decodes a Y axis of an m-th lower half layer based on decoding results of an X axis and a Z axis of an m1-th lower half layer; and a Z decoder which decodes a Z axis based on a decoding result of the Y axis of an m-th upper half layer and a decoding result of the X axis of an m-th lower half layer.

A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.