Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

A digital broadcasting system and a data processing method are disclosed. A receiving system of the digital broadcasting system includes a receiving unit, an SI handler, and a decoding unit. The receiving unit receives broadcast signals including mobile service data and main service data. The mobile service data configure a data group, and the data group includes a signaling information region in some of a plurality of data regions. The signaling information region may include TPC signaling data and FIC signaling data. The SI handler acquires channel configuration information of the mobile service data from the broadcast signal using pre-decided IP access information, and extracts encoding format information for each IP stream component within a corresponding virtual channel service RTP-packetized and received from the acquired channel configuration information. The decoding unit decodes the mobile service data of the corresponding IP stream component based upon the extracted encoding format information.

In one embodiment, a method includes reading packets of data from M parallel data tracks of a magnetic tape to obtain a plurality of (D+P)-symbol codewords which are logically arranged in nM encoded blocks, each packet including a row of an encoded block, where each encoded block includes an array having rows and columns of code symbols, wherein symbols of each of the (D+P)-symbol codewords are distributed over corresponding rows of the nM encoded blocks, decoding sub-blocks from rows and columns of a plurality of product codewords from the nM encoded blocks, each product codeword including a logical array of code symbols having the rows which include respective row codewords and the columns which include respective column codewords, where each sub-block includes a logical array having rows and columns of data symbols, combining the sub-blocks to form a block of data, and outputting the block of data.

A method of processing broadcast data in a broadcast transmitting system, the method includes randomizing, by a hardware processor, the broadcast data; first encoding, by the hardware processor, the randomized broadcast data to add first parity data for first forward error correction; second encoding, by the hardware processor, the first-encoded broadcast data to add second parity data for second forward error correction; permuting the second-encoded broadcast data; block interleaving, by the hardware processor, the permuted broadcast data; third encoding signaling information for signaling the broadcast data to add parity data; fourth encoding the third-encoded signaling information at a code rate; block interleaving the fourth-encoded signaling information; modulating the block-interleaved broadcast data and the block-interleaved signaling information; and transmitting a broadcast signal including the modulated broadcast data and the modulated signaling information.

Memory circuit defect correction in accordance with one aspect of the present description, logically divides a block of data bits into a plurality of data bit sections, each data bit section to be written into and stored in an associated memory section of a block of memory logically divided into a plurality memory sections. In one embodiment, for each data bit section and its associated memory section, the logical values of all the user data bits of the data bit section are selectively flipped so that the logical value of a user data bit to be written into a defective bitcell, matches the fixed read output of a defective bit cell. A bitcell in each memory section may be utilized to set a flip-flag to indicate whether or not the data bits of the memory section have been flipped. Other aspects are described herein.

Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.

Forward Error Correction technique: parity vectors are computed such that each parity vector spans multiple FEC frames; in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and the parity vectors are staggered with respect to any sequence in which the FEC frames are processed. Values of decoded bits of a first frame are deduced from known bits of a first parity vector having an effective length of one frame. For parity vectors having an effective length greater than one frame, a Log Likelihood Ratio of each unknown bit associated with the first frame is updated based on known and unknown bits of each parity vector. First frame is decoded using deduced bit values and updated LLR values.

A DTV transmitting system includes a frame encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The frame encoder builds an enhanced data frame and adds parity data into the data frame. The frame encoder further divides the data frame into first and second sub-frames including first and second portions of the parity data, respectively, and permutes a plurality of the first sub-frames and a plurality of the second sub-frames, respectively. The randomizer randomizes enhanced data in the permuted sub-frames, and the block processor codes the randomized data at a rate of 1/N1. The group formatter forms a group of enhanced data having one or more data regions and inserts the 1/N1 coded data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into enhanced data packets.

A method for Error Correction Code (ECC) encoding includes receiving data to be encoded. The data is encoded to produce a composite code word that includes multiple component code words. Each component code word in at least a subset of the component code words is encoded in accordance with a respective component code and has at least one respective bit in common with each of the other component code words.