An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

A semiconductor device of an embodiment includes an ECC decoding processing circuit configured to perform ECC decoding on ECC frame data in a lateral direction of a product code frame, an RS decoding processing circuit configured to perform Reed-Solomon (RS) decoding on second frame data in a longitudinal direction of the product code frame, a memory M0 in which a syndrome generated for the ECC frame data decoded is stored, a memory M1 in which an RS syndrome generated for ECC frame data for which the ECC decoding has been successful is stored, and a memory D in which ECC frame data for which the ECC decoding has been failed is stored as frame data which cannot be corrected through decoding, and frame collection processing, and iterative correction processing of performing RS decoding on the uncorrected frame data collected in the frame collection processing are executed.

The present technology relates to an error correction circuit. According to the present technology, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device.

Devices and methods for enhancing forward error correction techniques for communications using chirp spread spectrum are disclosed. The method includes receiving a chirp signal having a plurality of chirps, identifying an N bit column that has an uncorrectable bit error, skipping the identified N bit column, decoding each remaining N bit column within the M×N matrix based on an error correction code and N−Q parity bits, decoding each M bit row within the M×N matrix based on the error correction code and M−D parity bits, determining that the uncorrectable error bit in the identified N bit column is remedied as a result of the decoding, and decoding the identified N bit column based on an error correction code and N−Q parity bits.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

One embodiment provides a system which facilitates data movement. The system allocates, in a volatile memory of a first storage drive, a first region to be accessed directly by a second storage drive or a first NIC. The first storage drive, the second storage drive, and the first NIC are associated with a first server. The system stores data in the first region. Responsive to receiving a first request from the second storage drive to read the data, the system transmits, by the first storage drive to the second storage drive, the data stored in the first region while bypassing a system memory of the first server. Responsive to receiving, from a third storage drive associated with a second server, a second request to read the data, the system retrieves, by the first NIC, the data stored in the first region while bypassing the system memory of the first server.

Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.

The present disclosure relates to a system and a method for data protection. In some embodiments, an exemplary method for data encoding includes: receiving a data bulk; performing an erasure coding (EC) encoding on the data bulk to generate one or more EC codewords; distributing a plurality of portions of each EC codeword of the one or more EC codewords across a plurality of solid-state drives (SSDs); performing, at each SSD of the plurality of SSDs, an error correction coding (ECC) encoding on portions of the one or more EC codewords distributed to the SSD to generate an ECC codeword; and storing, in each SSD of the plurality of SSDs, the ECC codeword.

Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

A method generates a frozen vector associated with a polar code codeword on the basis of a frozen matrix associated with a product code codeword, the frozen matrix being of size N.sub.c×N.sub.r. The method includes replicating a first matrix row of the frozen matrix N.sub.c times to generate an expanded matrix row; replicating a first matrix column of the frozen matrix N.sub.r times to generate an expanded matrix column; generating the frozen vector on the basis of the expanded matrix row and the expanded matrix column. The disclosure further provides a method for generating a frozen matrix associated with a product code codeword on the basis of a frozen vector associated with a polar code codeword, wherein the product code codeword comprises a matrix of size N.sub.c×N.sub.r, and the frozen vector comprises a vector of size N with a plurality of bits.