A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

A method for determining when to end a bit flipping algorithm during hard decision soft decoding in a low density parity check (LDPC) decoder includes: selecting a certain number of iterations as a first threshold; when the first threshold is reached, determining a highest variable node codeword for each iteration performed so far; comparing the highest variable node codewords with a second threshold; and when the value of the highest variable node codewords is less than or equal to the second threshold, ending the bit flipping algorithm.

Methods and apparatus for transmitting and receiving broadcast signals are provided. The method for transmitting a broadcast signal includes encoding mobile data for forward error correction (FEC), encoding signaling data, forming data groups including the encoded mobile data and the encoded signaling data and transmitting a signal frame that includes the data groups.

A non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.

A decoding device includes: a BP decoder that performs BP decoding on an input signal: a maximum likelihood decoder that performs maximum likelihood decoding on a signal subjected to the BP decoding; and a selector that selects one of the input signal, the signal subjected to the BP decoding, and a signal subjected to the maximum likelihood decoding. In a configuration of the decoding device, when a decoder is appropriately operated according to quality of data, a calculation scale can be reduced, and power consumption can be decreased.

A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoding is hard decision hard decoding using a bit-flipping algorithm. When it is determined that the syndrome weights begin to overlap, the method further includes: performing one more iteration in hard decision hard decoding mode; providing a power boost to the LDPC decoder; and switching to hard decision soft decoding mode.

In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.