An apparatus and a method for constituent code processing in polar successive cancellation list (SCL) decoding and a method thereof. The apparatus includes a processor configured to determine a number of r candidate paths, wherein r is an integer; determine path metrics PM.sub.t.sub.j of a codeword j for each candidate path t; and select r most probable paths based on the path metrics PM.sub.t.sub.j. The method includes determining q indicies min.sub.1, min.sub.2, . . . , min.sub.q of least reliable bits in the constituent code, wherein q is a number; determining a number of r candidate paths, wherein r is an integer; determining path metrics PM.sub.t.sub.j of a codeword j for each candidate path t; and selecting r most probable paths based on the path metrics PM.sub.t.sub.j.

A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.

An operation method of a first communication node in a communication system includes receiving a signal from a second communication node; demodulating the signal to obtain LLR values; calculating a first codeword based on the LLR values; selecting error patterns from among all error patterns based on Hamming weights; generating second codewords by applying the first codeword to each of the selected error patterns; and determining a codeword having a highest similarity to the first codeword among the second codewords as an optimal codeword.

Disclosed are devices, systems and methods for polar coding and decoding for correcting deletion and insertion errors caused by a communication channel. One exemplary method for error correction includes receiving a portion of a block of polar-coded symbols that includes d≥2 insertion or deletion symbol errors, the block comprising N symbols, the received portion of the block comprising M symbols; estimating, based on one or more recursive calculations in a successive cancellation decoder (SCD), a location or a value corresponding to each of the d errors; and decoding, based on estimated locations or values, the portion of the block of polar-coded symbols to generate an estimate of information bits that correspond to the block of polar-coded symbols, wherein the SCD comprises at least log.sub.2(N)+1 layers, each comprising up to d.sup.2N processing nodes arranged as N groups, each of the N groups comprising up to d.sup.2 processing nodes.

A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

There is provided a method of sequential list decoding of an error correction code (ECC) utilizing a decoder comprising a plurality of processors. The method comprises: a) obtaining an ordered sequence of constituent codes usable for the sequential decoding of the ECC; b) executing, by a first processor, a task of decoding a first constituent code, the executing comprising: a. generating decoding candidate words (DCWs) usable to be selected for decoding a subsequent constituent code, each DCW associated with a ranking; b. for the first constituent code, upon occurrence of a sufficiency criterion, and prior to completion of the generating all DCWs and rankings, selecting, in accordance with a selection criterion, at least one DCW; c) executing, by a second processor, a task of decoding a subsequent constituent code, the executing comprising processing data derived from the selected DCWs to generate data usable for decoding a next subsequent constituent code.

Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

Data communications and storage systems require error control techniques to be transferred successfully without failure. Polar coding has been used as a state-of-the-art forward error correction code for such an error control technique. However, the conventional decoding based on successive cancellation has a drawback in its poor performance and long latency to complete. Because the factor graph of polar codes has a lot of short cycles, a parallelizable belief propagation decoding also does not perform well. The method and system of the present invention provide a way to resolve the issues by introducing a protograph lifting expansion for a polar coding family so that highly parallelizable decoding is realized to achieve a high coding gain and high throughput without increasing the computational complexity and latency. The invention enables an iterative message passing to work properly by eliminating short cycles through a hill-climbing optimization of frozen bits allocation and permutation.

There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining a channel output. The channel output represents the encoded sequence as passed through a communications channel. The encoded sequence has been encoded using a polar code. The polar code is representable by a code diagram. The method comprises successively decoding the channel output into the decoded sequence by traversing the code diagram. The method comprises, whilst traversing the code diagram, determining a bit score term for each potential decoding decision on one or more bits being decoded. The method comprises, whilst traversing the code diagram, adding an adjustment term to each bit score term to form a candidate score for said each potential decoding decision. The successive decoding is repeated until all bits of the channel output have been decoded, resulting in at least two candidate decoded sequences. The method comprises discarding all but one of the at least two candidate decoded sequences, resulting in one single decoded sequence.

A system, method, and apparatus enabling synchronous and asynchronous data sources to be demapped from an oFrame container using a generic mapping system.