A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.

Provided is a method for decoding a staircase code. The method includes following steps: soft information updating is performed on S initial encoding blocks in a staircase code to obtain a first information block, and last S−T encoding blocks in the first information block and T newly-added encoding blocks are updated to obtain a second information block; decoding is performed on first T encoding blocks in the first information block and first S−T encoding blocks in the second information block to obtain a third information block; and following operations are repeatedly performed: S−T information blocks are selected, the soft information updating is performed to obtain S updated information blocks, and the S updated information blocks are used as a new second information block; and decoding is performed to obtain a new third information block, and information of first T blocks is outputted as the output of the decoder.

The present application provides a data processing method, a data processing device, a decoder, a network device and a computer-readable storage medium. The data processing method includes: classifying log likelihood ratio (LLR) elements according to a modulation mode, a preset decoder quantization threshold and a signal-to-noise ratio, to obtain a classification result; extracting feature information of each category in the classification result; calculating to obtain a scale factor according to the feature information of each category; and scaling the LLR elements according to the scale factor.

A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.

A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate P.sub.e0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximal subset of a current solution, and calculating a new bit error rate P.sub.enew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate P.sub.e0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.

A three-dimensional data encoding method includes: generating an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2; generating first encoded data by encoding a first branch using a first encoding process, the first branch having, as a root, a first node included in a first layer that is one of layers included in the N-ary tree structure; generating second encoded data by encoding a second branch using a second encoding process different from the first encoding process, the second branch having, as a root, a second node included in the first layer and different from the first node; and generating a bitstream including the first encoded data and the second encoded data.

A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.

Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.

A hardware efficient implementation of a threshold modified attenuated min-sum algorithm (TAMSA”) and a threshold modified offset min-sum algorithm (“TOMSA”) that improve the performance of a low density parity-check (“LDPC”) decoder by reducing the bit error rate (“BER”) compared to the conventional attenuated min-sum algorithm (“AMSA”), offset min-sum algorithm (“OMSA”), and the min-sum algorithm (“MSA”). Embodiments of the present invention preferably use circuit optimization techniques, including a parallel computing structure and lookup tables, and a field-programmable gate array (“FPGA”) or application specific integrated circuit (“ASIC”) implementation.