Patent classifications
H03M13/658
Codeword bit selection for rate-compatible polar coding
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an encoding device may determine a least reliable subset of information bits included in a set of information bits that includes a predefined active set of information bits to be encoded; may determine a codeword bit to be added to a codeword based at least in part on the least reliable subset of information bits, wherein adding the codeword bit to the codeword improves reliability of the least reliable subset of information bits; may add the codeword bit to the codeword; and may transmit the codeword. Numerous other aspects are provided.
LOW-DENSITY PARITY-CHECK DECODING WITH DE-SATURATION
A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.
METHOD AND DEVICE FOR DECODING STAIRCASE CODE, AND STORAGE MEDIUM
Provided is a method for decoding a staircase code. The method includes following steps: soft information updating is performed on S initial encoding blocks in a staircase code to obtain a first information block, and last S−T encoding blocks in the first information block and T newly-added encoding blocks are updated to obtain a second information block; decoding is performed on first T encoding blocks in the first information block and first S−T encoding blocks in the second information block to obtain a third information block; and following operations are repeatedly performed: S−T information blocks are selected, the soft information updating is performed to obtain S updated information blocks, and the S updated information blocks are used as a new second information block; and decoding is performed to obtain a new third information block, and information of first T blocks is outputted as the output of the decoder.
SIMPLIFIED CHECK NODE PROCESSING IN NON-BINARY LDPC DECODER
Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.
APPLICATION OF LOW-DENSITY PARITY-CHECK CODES WITH CODEWORD SEGMENTATION
A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
Method and apparatus for wireless communication using polarization-based signal space mapping
A polarization stream architecture is described. A transmitter may implement a reverse polarization stream to shape a first source signal in a first signal space to a first target signal in a second signal space. The reverse polarization stream is implemented as a cascade of reverse polarization steps. Each reverse polarization step includes a shuffle function, a split function, a scaling function and an offset function. Machine-learning techniques may be used to implement the scaling function and the offset function. A receiver may implement a polarization stream to recover the source signal.
ENCODER AND FLASH MEMORY CONTROLLER
For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.
System and method for decoding iterations and dynamic scaling
A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.
Dynamic Scaling of Channel State Information
Channel state information (CSI) scaling modules for use in a demodulator configured to demodulate a signal received over a transmission channel, the demodulator comprising a soft decision error corrector (e.g. LDPC decoder) configured to decode data carried on data symbols of the received signal based on CSI values. The CSI scaling module is configured to monitor the performance of the soft decision error corrector and in response to determining the performance of the soft decision error corrector is below a predetermined level, dynamically select a new CSI scaling factor based on the performance of the soft decision error corrector.
Device, system and method for determining bit reliability information
Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.