Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.

Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuity to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.

Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

Methods and apparatus are disclosed for decoding low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers. The apparatus includes a decoder having circuitry to decode, layer by layer, a LDPC codeword utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword, the functional adjustments including layer specific parameters for at least two layers of the parity check matrix associated with the LDPC codeword.

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

A system implements adaptive desaturation for the min-sum decoding of LDPC codes. Specifically, when an-above threshold proportion of messages from check nodes to variable nodes (CN-to-VN messages) are saturated to a maximum fixed-precision value, all CN-to-VN messages are halved. This facilitates the saturation of correct messages and boosts error correction over small trapping sets. The adaptive desaturation approach reduces the error floor by orders of magnitudes with negligible add-on circuits.

Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.

A low density parity check (LDPC) decoder, including a memory configured to store a log-likelihood ratio (LLR) value of bits output from a demapper, and an LLR message exchanged between a variable node and an inspection node. The LDPC decoder further includes a node processor configured to select a decoding algorithm from a first algorithm and a second algorithm based on a code rate of an LDPC code, and decode the LLR message based on the selected decoding algorithm.

A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.