A data formatting module of a low voltage drive circuit (LVDC) includes a sample and hold circuit, an interpreter, a first buffer, a digital to digital converter circuit, and a data packeting circuit. The sample and hold circuit is operable to sample and hold an n-bit digital value of filtered digital data to produce an n-bit sampled digital data value. The interpreter is operable to convert the n-bit sampled digital data value into interpreted n-bit sampled digital data. The interpreter is operable to write the interpreted n-bit sampled digital data into the first buffer in accordance with a write clock until a digital word is formed. The digital to digital converter circuit is operable to format the digital word to produce a formatted digital word. The data packeting circuit is operable to generate a data packet from the formatted digital word and output the data packet as received digital data.

Described herein are systems configured for carrier aggregation. Systems include a multiplexing circuit having a filter assembly, switching circuit with a switching path, and a switchable impedance. The filters can be designed so that when operated simultaneously (e.g., during multi-band operation) the same inductance can be used allowing the switching network to switch in a particular inductance into the path. The described systems can include an inductance that is coupled to an output port so that when operating in single-band mode, the different paths share the same inductance. Relative to other solutions, the described systems can improve performance (e.g., reduce insertion loss), reduce the number of components in the associated module, reduce manufacturing costs, and the like.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.

A radio frequency circuit for processing a radio frequency signal. The circuit comprises a variable frequency oscillator system and a radio frequency signal processing circuit arranged to process a radio frequency signal using the output of the variable frequency oscillator system. A digitiser is arranged to receive the output of the radio frequency signal processing circuit and generate a digitised signal. A phase noise capture circuit is arranged to capture the phase noise in the output of the variable frequency oscillator system. The radio frequency circuit is arranged to compensate for the effect of the phase noise in the output of the variable frequency oscillator system on the output of the radio frequency signal processing circuit, by digitally processing the digitised signal generated by the digitiser using the output of the phase noise capture circuit.

A communication system is provided, which includes a power amplifier, a receive-end filter, an ADC, an output simulation circuit, and a predistortion circuit. The power amplifier amplifies a RF input signal to generate a RF output signal. The RF input signal is generated according to a baseband signal. The receive-end filter filters a feedback signal generated according to the RF output signal to output a filtered feedback signal. A bandwidth of the filtered feedback signal is at least 3 to 5 times a bandwidth of the RF input signal. The ADC converts the filtered feedback signal to a digital input signal. The output simulation circuit generates, according to the digital input signal and the baseband signal, a reference signal simulating the RF output signal. The predistortion circuit builds a predistortion model according to the reference signal.

A low voltage drive circuit (LVDC) includes a data splitter operable to split transmit digital data into a plurality of streams of digital data. The LVDC further includes a plurality of signal generators operable to receive the plurality of streams of digital data at a plurality of data rates and generate a plurality of analog outbound data signals for the plurality of streams of digital data. A first signal generator receives a first stream of digital data of the plurality of streams of digital data at a first data rate. A second signal generator receives a second stream of digital data of the plurality of streams of digital data at a second data rate. The LVDC further includes a signal combiner operable to combine the plurality of analog outbound data signals into analog outbound data and a drive sense circuit operable to drive the analog outbound data onto a bus.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion a compensation circuit and a digital to analog conversion circuit. The compensation circuit includes a filter configured to provide roll off compensation in a baseband frequency using real coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal so that the second digital signal can be filtered by the filter using the real coefficients.

A method of operating a communications system includes receiving a signal at a digital predistorter (DPD), introducing predistortion to the signal using the DPD, and converting the predistorted signal to an analog signal using a digital-to-analog converter having a first bandwidth. The method also includes amplifying the analog signal, sampling the amplified signal using an analog-to-digital converter having a second bandwidth less than the first bandwidth, and extracting coefficients of the DPD from the sampled signal.

The present disclosure generally relates to multi-stage digital converters, including multi-stage digital down-converters (DDCs) and multi-stage digital up-converters (DUCs). In at least one example, the multi-stage digital down converter (DDC) comprises a plurality of stages, each stage comprising a frequency mixer and a decimation filter, and at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and decimation filter. In another example, the multi-stage digital up converter (DUC) comprises a plurality of stages, each stage comprising a frequency mixer and interpolation filter; at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and the interpolation filter.

A method for digital resampling in a digital communications receiver is described. The method comprises selecting whole samples of a received input signal in the time domain and implementing sub-sample digital interpolation in the frequency domain. This amounts to performing the time shift of the interpolation process in the frequency domain. The method may be performed in conjunction with the operation of a polarisation recovery filter. A digital communications receiver is also provided the receiver being arranged to perform frequency domain sub-sample interpolation on an input data signal.