A demodulator 100 includes: an AD conversion section 10 that converts a received signal RF in an analogue form to a digital signal; a noise removal section 40 that is connected to a back side of the AD conversion section 10 to detect and remove a noise from an input signal; decimation filters 52 and 54 that are connected to a back side of the noise removal section 40 and reduce a data rate of an input signal; and a demodulation section 60 that is connected to back sides of the decimation filters 52 and 54 and demodulates an input signal. The decimation filters 52 and 54 are connected to the back side of the noise removal section 40, which provides a demodulator less subject to degradation of a signal wave.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

Provided is a wireless signal receiver including: an analog-digital converter (ADC) converting an analog RF signal into a digital baseband signal; and a sub-sampling block dividing and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal by using a relative sample delay difference between the first and second path signals, wherein the first path signal is a signal obtained by adjusting a sample delay and sampling rate of the digital baseband signal, and the second path signal is a signal obtained by filtering without adjusting the sampling rate of the digital baseband signal.

A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.

A method and system for extracting values representative of modulation signal components from a modulated signal, the modulated signal containing a modulation signal, including developing a local clock signal which correlates in time to the modulated signal and includes a number of phase sectors per cycle and converting the modulated signal into a current that is representative of the signal and routing the current to the inverting input of an amplifier and charging one of a plurality of capacitive devices during each phase sector and sequentially connecting the capacitive devices between the output of the amplifier and the inverting input of the amplifier in non-overlapping sequences, the total of sequences being equal to one full cycle of the clock.

A heterodyne receiver structure comprises a frequency conversion block arranged to convert an incoming analog radio frequency (RF) signal to an analog intermediate frequency (IF) signal; a filter block arranged to filter said analog IF signal; and an analog-to-digital (AD) converter block arranged to convert said filtered analog IF signal to a digital signal, wherein the AD converter block (309) is arranged to convert the filtered analog IF signal to the digital signal by using a sampling frequency (fs) which is at least N times a maximum bandwidth of the filtered analog IF signal, wherein the frequency spectrum from zero to the sampling frequency is divided into N frequency zones of equal width, wherein N is an even positive number higher than two; the frequency conversion block (304) is arranged to convert the incoming analog RF signal to the analog IF signal such that the analog IF signal is located in any of the N/2-1 frequency zones having lowest frequency; and the filter block (306-308) is arranged to low pass the analog IF signal such that any disturbing signal located in a zone, which would have a mirror image after the AD conversion in the zone, in which the analog IF signal is located, is filtered away, wherein the heterodyne receiver structure further comprises a digital signal processing block (311) arranged to filter said digital signal.

Systems, methods and devices are disclosed for a variable-rate true-time delay (VR-TTD) decimator for receiving an input data signal and providing an output decimated signal. The VR-TTD decimator may comprise: a VR-TTD decimator input for receiving the input data signal; and a VR-TTD decimator output for outputting the output decimated signal; a numerically controlled oscillator (NCO) for receiving a time delay control signal and a desired rate signal and for controlling coarse filtering, fine filtering and decimation of the input data signal; and an accumulator for generating the output decimated signal, wherein the accumulator comprises a plurality of shift registers, controlled by the NCO. The system may comprise a beamformer for providing an output signal coherently summed from a plurality of paths, where each path comprises a VR-TTD decimator for providing VR-TTD to the respective signals of the plurality of paths.

The present disclosure generally relates to multi-stage digital converters, including multi-stage digital down-converters (DDCs) and multi-stage digital up-converters (DUCs). In at least one example, the multi-stage digital down converter (DDC) comprises a plurality of stages, each stage comprising a frequency mixer and a decimation filter, and at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and decimation filter. In another example, the multi-stage digital up converter (DUC) comprises a plurality of stages, each stage comprising a frequency mixer and interpolation filter; at least one controller coupled to one or more of the plurality of stages and operable to control one of the frequency mixer and the interpolation filter.