The total sum of wiring lengths between reception filters and low-noise amplifiers is reduced. A high frequency module includes a mounting board, a plurality of inductors, a plurality of reception filters, and an IC component. The plurality of inductors are mounted on a first main surface of the mounting board. The plurality of reception filters are mounted on the first main surface of the mounting board. The IC component is mounted on a second main surface of the mounting board and includes a low-noise amplifier. A rectangular region in which the plurality of inductors are positioned overlaps with the IC component when viewed in plan from a thickness direction of the mounting board. An electronic component that is closest to each of three or more sides out of four sides of the rectangular region is at least one of the plurality of reception filters.

A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

A method for improving frequency response of a high-speed data acquisition device includes sampling signals received at an input of the high-speed data acquisition device at a first sampling rate and generating a digital data stream representative of the sampled input signals. The digital data stream is interpolated to generate an interpolated digital signal with a higher sample rate than the first sampling rate, and one or more finite impulse response (FIR) filters are applied to the interpolated digital signal to generate a filtered digital signal. The filtered digital signal corrects for: parasitic and/or expected response of elements from the network of resistors and capacitors in the anti-aliasing filter in the high-speed data acquisition device, and select anti-aliasing filter response characteristics. The filtered digital signal is decimated to reduce the sampling rate of the filtered digital signal and generate a decimated digital signal.

A signal processing device is provided. The signal processing device includes a proximal end device, a connection unit, and a distal end device. The proximal end device generates a first radio frequency signal. The connection unit is coupled to the proximal end device and receives and transmits the first radio frequency signal. The distal end device is coupled to the connection unit, receives the first radio frequency signal, performs a power detection on the first radio frequency signal to generate a detection signal, generates a control signal according to a comparison result of the detection signal and a predetermined reference value, and transmits the control signal to the connection unit. The proximal end device further receives the control signal through the connection unit, and adjusts the first radio frequency signal according to the control signal so as to generate a second radio frequency signal.

A radio frequency module has a substrate, a first chip inductor, an integrated circuit, and a first amplifier connected to the first chip inductor. The first chip inductor is on a first main surface of the substrate and the integrated circuit is on a second main surface of the substrate, the second main surface being opposite the first main surface. The integrated circuit includes the first amplifier. When the substrate is viewed from a direction perpendicular to the first main surface of the substrate, the first chip inductor at least partially overlaps the integrated circuit.

Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

A signal processing device includes: a processor; and a memory having instructions. When executed by the processor, the instructions cause the signal processing device to perform operations including: converting a first signal that is a time domain signal into a second signal that is a frequency domain signal in response to reception of the first signal, the first signal containing noise superimposed on a broadcast electric signal derived from a broadcast electromagnetic wave, the noise having peaks of amplitude at regular frequency intervals in the frequency domain; calculating a frequency interval between the peaks of the noise in the frequency domain based on a correlation of the second signal; determining a frequency shift amount in the frequency domain based on the frequency interval; and shifting a frequency of the second signal by the frequency shift amount to create a frequency-shifted signal.

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

A signal processing device is provided. The signal processing device includes a proximal end device, a connection unit, and a distal end device. The proximal end device generates a first radio frequency signal. The connection unit is coupled to the proximal end device and receives and transmits the first radio frequency signal. The distal end device is coupled to the connection unit, receives the first radio frequency signal, performs a power detection on the first radio frequency signal to generate a detection signal, generates a control signal according to a comparison result of the detection signal and a predetermined reference value, and transmits the control signal to the connection unit. The proximal end device further receives the control signal through the connection unit, and adjusts the first radio frequency signal according to the control signal so as to generate a second radio frequency signal.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.