Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

A signal processing device includes: a processor; and a memory having instructions. When executed by the processor, the instructions cause the signal processing device to perform operations including: converting a first signal that is a time domain signal into a second signal that is a frequency domain signal in response to reception of the first signal, the first signal containing noise superimposed on a broadcast electric signal derived from a broadcast electromagnetic wave, the noise having peaks of amplitude at regular frequency intervals in the frequency domain; calculating a frequency interval between the peaks of the noise in the frequency domain based on a correlation of the second signal; determining a frequency shift amount in the frequency domain based on the frequency interval; and shifting a frequency of the second signal by the frequency shift amount to create a frequency-shifted signal.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

The present disclosure provides a signal calibration method, apparatus and device generated based on an imbalance of I path and Q path. The method includes sending a cosine signal and a sine signal through a signal generator, transmitting the cosine signal and the sine signal in the I path and the Q path respectively, the cosine signal and the sine signal being configured to loop back to a signal receiving direction after passing through a transmitting amplifier; processing a signal obtained by a down converter in the signal receiving direction; performing a phase adjustment and an amplitude adjustment by adjusting the signal generator, gain amplifiers of I path and Q path analog domains, and a corresponding digital domain, so as to determine an appropriate phase cancellation value and an appropriate amplitude cancellation value for an image signal; and calibrating the image signal corresponding to the signal to be calibrated.

An operation method of an in-band full duplex (IFD) transceiving apparatus including a receiving end, a transmitting end, a digital self-interference cancellation (DSIC) processing unit, and a digital SI cancellation unit may comprise generating, by the DSIC processing unit, signal shaping coefficients for wave shaping of a signal of the transmitting end; generating, by the DSIC processing unit, channel estimation coefficients for cancellation of a self-interference signal in a reception signal of the receiving end; forming, by the DSIC processing unit, a transmission signal based on the signal shaping coefficients; and generating, by the DSIC processing unit, a control signal for cancellation of the self-interference signal in the reception signal based on the channel estimation coefficients.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.

An amplifier circuit unit of a radio frequency module is mounted on a substrate with a first external terminal interposed therebetween, a switch circuit unit is mounted on the substrate with a second external terminal interposed therebetween, and a matching circuit unit is mounted on the substrate with a first terminal and a second terminal interposed therebetween. The first terminal is electrically connected to the second external terminal of the switch circuit unit, and the second terminal is electrically connected to the first external terminal of the amplifier circuit unit. When viewed from a direction perpendicular to one main surface of the substrate, the first terminal is superposed with the second external terminal of the switch circuit unit, and the second terminal is superposed with the first external terminal of the amplifier circuit unit.

A method for correcting RDS demodulation in a vehicle radio system including a digital core with an RDS demodulation block, a numerically controlled oscillator, a digital mixer that mixes the input signals with the output of the numerically controlled oscillator, a low-pass filter for recovering baseband RDS signals including a sequence of symbols, and a phase-estimating block configured to estimate a phase deviation of the baseband signal. The method including a first correction acting, depending on the estimation of the phase deviation of the baseband signal, on a phase equalizer, downstream of the low-pass filter, in order to cancel out the phase deviation, and optionally a second correction forming a feedback loop and acting on the numerically controlled oscillator depending on the drift in the phase deviations of the baseband signal.

An amplifier circuit unit of a radio frequency module is mounted on a substrate with a first external terminal interposed therebetween, a switch circuit unit is mounted on the substrate with a second external terminal interposed therebetween, and a matching circuit unit is mounted on the substrate with a first terminal and a second terminal interposed therebetween. The first terminal is electrically connected to the second external terminal of the switch circuit unit, and the second terminal is electrically connected to the first external terminal of the amplifier circuit unit. When viewed from a direction perpendicular to one main surface of the substrate, the first terminal is superposed with the second external terminal of the switch circuit unit, and the second terminal is superposed with the first external terminal of the amplifier circuit unit.