Patent classifications
H04B1/0046
EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR
Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.
VARIABLE-RATE DECODER-BASED WIRELESS RECEIVER
The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a structure operative to receive a plurality of analog signals, a signal encoding configured to encode the plurality of received analog signals into a single encoded analog composite signal based on a coding scheme having a low code rate, a signal reconstruction module configured to convert the single encoded digital composite signal into a high encode rate digital composite signal in accordance with the coding scheme having a high code rate. In addition, a signal decoder configured to decode the digital composite signals based on the coding scheme having the high code rate and to output digital signals corresponding to the received plurality of analog signals.
Method for determining MIMO detection matrix of scheduled UE
The present application discloses a method and an apparatus for signal processing. In the present application, since a front end device in a base station system performs MIMO detection and related baseband-processing of a time domain signal received from an antenna unit and transmits the signal that is baseband-processed to a back end device of the base station system, the back end device merely performs other baseband processing, apart from the MIMO detection and the related baseband processing. Compared with the prior art, the embodiments of the present application move some of the baseband processing forward to be implemented on a front end device such that only the data of each scheduled user with less redundancy are required to be transmitted in an interface between the front end device and a backend device, reducing the pressure on the rate of data transmission between the front end device and the back end device.
METHOD AND APPARATUS FOR SIGNAL PROCESSING
The present application discloses a method and an apparatus for signal processing. In the present application, since a front end device in a base station system performs MIMO detection and related baseband-processing of a time domain signal received from an antenna unit and transmits the signal that is baseband-processed to a back end device of the base station system, the back end device merely performs other baseband processing, apart from the MIMO detection and the related baseband processing. Compared with the prior art, the embodiments of the present application move some of the baseband processing forward to be implemented on a front end device such that only the data of each scheduled user with less redundancy are required to be transmitted in an interface between the front end device and a backend device, reducing the pressure on the rate of data transmission between the front end device and the back end device.
INTEGRATED MIXED-SIGNAL RF TRANSCEIVER WITH ADC, DAC, AND DSP AND HIGH-BANDWIDTH COHERENT RECOMBINATION
An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications capable of flexibly processing high-bandwidth and low-bandwidth RF input signal(s). The RF transceiver may selectively distribute high-bandwidth RF input signals among one or more DSP pipelines for parallel processing of the RF input signals, and the RF transceiver may coherently recombine the processed signals from the one or more DSP pipelines to generate an RF output signal. The ADDA RF transceiver includes one or more ADCs, DSPs, and DACs, all on one or more ASICs, FPGAs, or modular electronic devices in a single semiconductor package. Further, the RF transceiver is radiation tolerant at the module, circuit, and/or system level for high availability and reliability in the ionizing radiation environment present in the space environment.
EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR
Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.
Multi-rate crest factor reduction
A computer-implemented method for reducing crest factor by an electronic device includes: receiving a plurality of first samples of a first input signal. The plurality of first samples are generated at a first sampling rate. A first peak detection is performed based on the plurality of first samples to generate a plurality of first peak detection output samples. A plurality of first windowing input samples are generated at a second sampling rate by downsampling the plurality of first peak detection output samples. A plurality of first windowing output samples are generated based on the plurality of first windowing input samples. A plurality of first peak reduction samples are generated at the first sampling rate by upsampling the plurality of first windowing output samples. A first output signal is generated based on the plurality of first samples and the plurality of first peak reduction samples.
INTEGRATED MIXED-SIGNAL ASIC WITH ADC, DAC, AND DSP
An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
Transformation based filter for interpolation or decimation
A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.
Method of processing compressive sensing signal and apparatus for same
Disclosed is a method of receiving a compressive sensing signal and an apparatus for the same. According to an embodiment of the present disclosure, the method includes: receiving a signal processed using a predetermined dictionary set and a first sampling rate for each symbol group including one or more symbols; performing analog-to-digital conversion on the received signal at a second sampling rate that is lower than the first sampling rate; checking compressed measurement information from the signal on which analog-to-digital conversion is performed; and reconstructing values of the symbols included in the symbol group, which correspond to the compressed measurement information, on the basis of the predetermined dictionary set.