An output signal generation device includes: two or more signal output blocks that each include two or more serial output circuits and a signal multiplex unit, the serial output circuits controlling amplitudes of data signals having different delay times and each outputting a first serial signal, the signal multiplex unit electrically multiplexing the first serial signals outputted from the two or more serial output circuits, and output a second serial signal obtained by electrical multiplex of the signal multiplex unit; and a phase correction unit that controls a phase of the second serial signal outputted from the two or more signal output blocks by changing the amplitude of the first serial signal outputted from the serial output circuit.

A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

A band pass filter is implemented utilizing Channelized Active Noise Elimination (CANE) in combining Finite Impulse Response (FIR) filtering into a radio frequency (RF) transmitter, or transmission path. The FIR filtering is performed in a combination of multiple conversion paths of delay units, vector modulators and PAs so that the low pass characteristics of the FIR filter are upconverted on the adjacent frequency of the carrier to form a band pass filter at the output of the transmitter. Use of CANE avoids the need of high sampling rates, while also eliminating the need of either broad bandwidth delay lines or modulated power amplifiers. The technique is well-suited for suppression of the quantization noise generated in RF transmitters with bitstream modulations such as the Envelope Delta Sigma Modulation (EDSM).

A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance is adjusted to match one of an impedance of the differential antenna, an impedance of the first PA, and an impedance of the second PA, based on the ripples detected by the ripple detector.

This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

The present disclosure relates to a front-end system for a radio device comprising: a charge generator circuit arranged for receiving a digital baseband signal, a first converter circuit arranged for calculating at least one charge value based on the digital baseband signal, a second converter circuit arranged for converting the at least one charge value into at least one electrical charge, and a modulator circuit arranged for generating a radio frequency signal based on the at least one electrical charge and at least one local oscillator signal.

A radio frequency (RF) multiplexer circuit is provided. The multiplexer includes a first circuit coupled between a first input terminal and a first output terminal. The first circuit is configured and arranged to transfer a first RF signal coupled at the first input terminal to the first output terminal as a first output signal when a first control signal is at a first logic value. The multiplexer includes a second circuit coupled between a second input terminal and the first output terminal. The second circuit is configured and arranged to transfer a second RF signal coupled at the second input terminal to the first output terminal as a second output signal having a gain higher than the gain of the second RF signal when the first control signal is at a second logic value.

A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

This disclosure describes apparatuses, methods, and techniques for supporting multiple protocols with selective amplification, such as 5 GHz Wi-Fi®, 2.4 GHz Wi-Fi®, 2.4 GHz Bluetooth Classic®, 2.4 GHz BLE®, and/or 2.4 GHz IEEE 802.15.4 (e.g., Thread® or ZigBee®) protocols. In more detail, the disclosure describes a multi-protocol transceiver system that includes a front-end architecture, which enables the multi-protocol transceiver system to transmit and receive the wireless communication signals according to the multiple protocols. The multi-protocol transceiver system may utilize one or more antennas to transmit and receive the multiple protocols.

An apparatus includes multiple signal paths for signal transmission, and control circuitry. The multiple signal paths include a first signal path and a second signal path. The first signal path is configured to convert a digital baseband signal to a first radio frequency (RF) signal having a first frequency and a first gain. The second signal path is configured to convert a digital baseband signal to a second RF signal having a second frequency and a second gain, wherein the second gain is less than the first gain. The control circuitry is coupled to the plurality of signal paths and is configured to receive one or more control signals to enable selective activation of at least one signal path of the plurality of signal paths.