A millimeter wave mobile phone antenna structure including: a plurality of antenna elements, each antenna element having a port; a plurality of signal acquisition units, each having a mixer and an analog-to-digital converter to produce a digital sampled signal of a sub-carrier signal output by each port; and a baseband signal processor, used for multiplying the digital sampled signal of each sub-carrier signal with a real time channel frequency response related weighting function and sum up the products to obtain a total output value of the antenna structure. The difference between the antenna structure of the present invention and the current millimeter-wave antenna structure of mobile phones is that: the present invention uses antenna elements instead of antenna arrays; and the antenna structure of the present invention provides multi-port output signals, rather than a single output digital, to facilitate the adaptability of received signals combining on the baseband end.

A millimeter wave mobile phone antenna structure including: a plurality of antenna elements, each antenna element having a port; a plurality of signal acquisition units, each having a mixer and an analog-to-digital converter to produce a digital sampled signal of a sub-carrier signal output by each port; and a baseband signal processor, used for multiplying the digital sampled signal of each sub-carrier signal with a real time channel frequency response related weighting function and sum up the products to obtain a total output value of the antenna structure. The difference between the antenna structure of the present invention and the current millimeter-wave antenna structure of mobile phones is that: the present invention uses antenna elements instead of antenna arrays; and the antenna structure of the present invention provides multi-port output signals, rather than a single output digital, to facilitate the adaptability of received signals combining on the baseband end.

Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

Example access network devices are described. One example access network device includes a signal processing apparatus. The signal processing apparatus includes a first power amplifier, a second power amplifier, a first filter, a second filter, and a combiner. The first filter filters a second signal obtained by the first power amplifier, to obtain a first sub-signal belonging to a first frequency band and a second sub-signal belonging to a second frequency band. The second filter filters a fourth signal obtained by the second power amplifier, to obtain n sub-signals including at least a third sub-signal belonging to a third frequency band. The combiner combines the first sub-signal and i sub-signals in the n sub-signals based on a preset condition, to obtain a first combined signal. The communication module sends the first combined signal by using a first port, and sends the second sub-signal by using a second port.

Example access network devices are described. One example access network device includes a signal processing apparatus. The signal processing apparatus includes a first power amplifier, a second power amplifier, a first filter, a second filter, and a combiner. The first filter filters a second signal obtained by the first power amplifier, to obtain a first sub-signal belonging to a first frequency band and a second sub-signal belonging to a second frequency band. The second filter filters a fourth signal obtained by the second power amplifier, to obtain n sub-signals including at least a third sub-signal belonging to a third frequency band. The combiner combines the first sub-signal and i sub-signals in the n sub-signals based on a preset condition, to obtain a first combined signal. The communication module sends the first combined signal by using a first port, and sends the second sub-signal by using a second port.

The present disclosure relates to a circuit including an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected to the input terminal and including a low-noise amplifier having an input coupled to the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and/or to the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

The present disclosure relates to a circuit including an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected to the input terminal and including a low-noise amplifier having an input coupled to the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and/or to the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

A multi-amplitude modulation receiver includes a signal coupler block coupled to a mixer array block receiving a first input signal from the signal coupler block and a second input from a LO circuit that provides N overlapping phase signals. Outputs of the N mixer elements are coupled to a baseband filter (BBF) block then to a decision threshold block including decision threshold elements including a signal input and at least one comparator receiving at least one V.sub.TH value. A phase ordering and mapper block selects M out of the N phases. A digital logic and control block is coupled to control a filter gain and corner frequency of the BBF block and control the V.sub.TH value for the decision threshold block which compares a signal received to the V.sub.TH value. Outputs from the decision threshold block are coupled inputs of an M-input decision combiner which provides a single data output.