A full duplex, low latency, near field data link controls a static and/or dynamic resonant induction, wireless power transfer system used for recharging electric vehicles and other electrically powered devices. A coherent transponder configuration enables low complexity synchronous detection and positive rejection of signals originating from nearby and adjacent vehicles. A reference crystal oscillator in the ground side apparatus provides frequency synchronization for both the forward and the return data links. Transmission is by means of near field magnetic induction between pairs of loop antennas which, together with the effective waveguide below cutoff structure comprised by the vehicle underbody and the ground surface, largely restrict signal propagation to the area in the immediate vicinity of the system antennas.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

Aspects relate to correcting Inphase/Quadrature (I/Q) imbalances across multiple wireless elements such as multiple receive elements or multiple transmit elements. In one example implementation, I/Q imbalances can be corrected using a digital circuit provided within a digital portion of a direct conversion wireless element (upconversion or downconversion) that implements only two multiplications and one addition per pair of I and Q samples.

Aspects relate to correcting Inphase/Quadrature (I/Q) imbalances across multiple wireless elements such as multiple receive elements or multiple transmit elements. In one example implementation, I/Q imbalances can be corrected using a digital circuit provided within a digital portion of a direct conversion wireless element (upconversion or downconversion) that implements only two multiplications and one addition per pair of I and Q samples.

A signal mixing circuit device includes a first mixer, a second mixer and a signal amplifying circuit serially connected to the first mixer; the first mixer includes an RF signal input terminal for receiving an RF signal, LO signal input terminals for sampling a first and second LO signals, a first mixed-signal output terminal for outputting a first mixed signal and a second mixed-signal output terminal for outputting a second mixed signal; the second mixer includes an input terminal connected to a capacitor, two mixed-signal output terminals respectively connected to the first and second mixed-signal output terminals of the first mixer, LO signal input terminals for inversely sampling the first and second LO signals. With the double-balance nature of the second mixer core, the noise at the LO signal input terminals of the first mixer can be cancelled. A receiver includes the signal mixing circuit device is also disclosed.

A signal mixing circuit device includes a first mixer, a second mixer and a signal amplifying circuit serially connected to the first mixer; the first mixer includes an RF signal input terminal for receiving an RF signal, LO signal input terminals for sampling a first and second LO signals, a first mixed-signal output terminal for outputting a first mixed signal and a second mixed-signal output terminal for outputting a second mixed signal; the second mixer includes an input terminal connected to a capacitor, two mixed-signal output terminals respectively connected to the first and second mixed-signal output terminals of the first mixer, LO signal input terminals for inversely sampling the first and second LO signals. With the double-balance nature of the second mixer core, the noise at the LO signal input terminals of the first mixer can be cancelled. A receiver includes the signal mixing circuit device is also disclosed.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A transceiver includes a transmitter, a frequency synthesizer coupled to the transmitter, a receiver coupled to the frequency synthesizer and a voltage sensor; and a digital controller coupled to the voltage sensor, the receiver, and the transmitter, wherein based on a DC voltage measurement of an IF signal made by the voltage sensor, a relative phase adjustment occurs of a relative phase associated with a local oscillator (LO) port and a radio frequency (RF) port of the receiver.