Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

Aspects of the present disclosure relate to methods and apparatus for location encoding for secondary synchronization signals (SSS) to convey additional information, such as a current symbol number. According to aspects, a method is provided herein for wireless communications that may be performed, for example, by a base station (BS). The method generally includes selecting frequency resources to use for transmitting synchronization signals in a symbol of a frame, wherein the frequency resources are selected based on a mapping of frequency resources to a location of the symbol within the frame; and transmitting synchronization signals to at least one user equipment (UE) according to the mapping. As a result, the UE may receive synchronization signals, determine a location of the current symbol in a frame based on the mapping, and synchronize to the BS based on the determined location of the current symbol. Numerous other aspects are provided.

A method of receiving two chip-by-chip multiplexed CSK signals (e.g., GNSS signals) and searching for a non-CSK signal with optimal performance at a given digit capacity of a sampling memory resided in parallel correlators. For CSK signals Prompt, Early and Late results for each of possible code shift are calculated as different sums of four punctured convolutions. Depending on configuration, the method allows to receive both multiplexed CSK signals with lesser quality or one of the CSK signals with better quality. The method can be implemented as an apparatus with four punctured correlators, a set of multipliers by 1 or 2.sup.N, another set of multipliers by 1 or 0, summers of four input to one result, a RAM, searchers of maximum, and conditional commutators.

A method of receiving two chip-by-chip multiplexed CSK signals (e.g., GNSS signals) and searching for a non-CSK signal with optimal performance at a given digit capacity of a sampling memory resided in parallel correlators. For CSK signals Prompt, Early and Late results for each of possible code shift are calculated as different sums of four punctured convolutions. Depending on configuration, the method allows to receive both multiplexed CSK signals with lesser quality or one of the CSK signals with better quality. The method can be implemented as an apparatus with four punctured correlators, a set of multipliers by 1 or 2.sup.N, another set of multipliers by 1 or 0, summers of four input to one result, a RAM, searchers of maximum, and conditional commutators.

A sensor controller includes a transmitter configured to transmit an uplink signal including a first partial signal and a second partial signal. The transmitter is configured to transmit the first partial signal by direct spreading using a first spread code and transmit the second partial signal by direct spreading using a second spread code which is different from the first spread code and which has an identical chip time length to the first spread code. An active stylus includes a receiver configured to receive an uplink signal including a first partial signal and a second partial signal. The receiver is configured to synchronize with the uplink signal by detecting the first partial signal using a first spread code and thereafter detect the second partial signal using a second spread code, which is different from the first spread code and has an identical chip time length to the first spread code.

A sensor controller includes a transmitter configured to transmit an uplink signal including a first partial signal and a second partial signal. The transmitter is configured to transmit the first partial signal by direct spreading using a first spread code and transmit the second partial signal by direct spreading using a second spread code which is different from the first spread code and which has an identical chip time length to the first spread code. An active stylus includes a receiver configured to receive an uplink signal including a first partial signal and a second partial signal. The receiver is configured to synchronize with the uplink signal by detecting the first partial signal using a first spread code and thereafter detect the second partial signal using a second spread code, which is different from the first spread code and has an identical chip time length to the first spread code.

A method of receiving two chip-by-chip multiplexed CSK signals (e.g., GNSS signals) and searching for a non-CSK signal with optimal performance at a given digit capacity of a sampling memory resided in parallel correlators. For CSK signals Prompt, Early and Late results for each of possible code shift are calculated as different sums of four punctured convolutions. Depending on configuration, the method allows to receive both multiplexed CSK signals with lesser quality or one of the CSK signals with better quality. The method can be implemented as an apparatus with four punctured correlators, a set of multipliers by 1 or 2.sup.N, another set of multipliers by 1 or 0, summers of four input to one result, a RAM, searchers of maximum, and conditional commutators.

A method of receiving two chip-by-chip multiplexed CSK signals (e.g., GNSS signals) and searching for a non-CSK signal with optimal performance at a given digit capacity of a sampling memory resided in parallel correlators. For CSK signals Prompt, Early and Late results for each of possible code shift are calculated as different sums of four punctured convolutions. Depending on configuration, the method allows to receive both multiplexed CSK signals with lesser quality or one of the CSK signals with better quality. The method can be implemented as an apparatus with four punctured correlators, a set of multipliers by 1 or 2.sup.N, another set of multipliers by 1 or 0, summers of four input to one result, a RAM, searchers of maximum, and conditional commutators.