A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

An example method of calibrating signals in an antenna array includes generating a calibration signal at a first radio sub unit (RSU), transmitting the calibration signal through a transmission path of a radio front end (RFE) of the first RSU, and receiving the calibration signal in a coupling and distribution layer of the first RSU. The method further includes providing the calibration signal from the coupling and distribution layer of the first RSU directly to a coupling and distribution layer of a second RSU, and processing the calibration signal at the second RSU.

An example method of calibrating signals in an antenna array includes generating a calibration signal at a first radio sub unit (RSU), transmitting the calibration signal through a transmission path of a radio front end (RFE) of the first RSU, and receiving the calibration signal in a coupling and distribution layer of the first RSU. The method further includes providing the calibration signal from the coupling and distribution layer of the first RSU directly to a coupling and distribution layer of a second RSU, and processing the calibration signal at the second RSU.

To achieve a filter circuit that is configured to have a good frequency rejection characteristic and suppress an increase in size due to mounting, in a more preferred aspect. A filter circuit includes a first signal line that is arranged to extend longitudinally, and a second signal line that is arranged to extend in parallel with the first signal line, in which the second signal line has one end that is electrically connected to the first signal line, and the other end that is open, in a longitudinal direction, and a length in the longitudinal direction that is determined according to a frequency of a signal to be blocked of signals transmitted through the first signal line.

To achieve a filter circuit that is configured to have a good frequency rejection characteristic and suppress an increase in size due to mounting, in a more preferred aspect. A filter circuit includes a first signal line that is arranged to extend longitudinally, and a second signal line that is arranged to extend in parallel with the first signal line, in which the second signal line has one end that is electrically connected to the first signal line, and the other end that is open, in a longitudinal direction, and a length in the longitudinal direction that is determined according to a frequency of a signal to be blocked of signals transmitted through the first signal line.

Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

A symbol-determining device according to an embodiment includes: a transmission line shortening unit that multiplies each symbol value of a symbol array that is part of an input signal by a tap gain of a linear digital filter and outputs a symbol array representing a sum of values acquired through the multiplication; a transmission line estimating unit that estimates a transfer function of a transmission line using an adaptive nonlinear digital filter on the basis of a symbol array representing a state of the transmission line; an addition comparison processing unit that calculates a minimum value of a distance function in a Viterbi algorithm on the basis of a metric that is calculated on the basis of the output of the transmission line shortening unit and the transfer function; and a path tracing-back determination unit that performs symbol determination by tracing back a trellis path in the Viterbi algorithm on the basis of the minimum value of the distance function.

A symbol-determining device according to an embodiment includes: a transmission line shortening unit that multiplies each symbol value of a symbol array that is part of an input signal by a tap gain of a linear digital filter and outputs a symbol array representing a sum of values acquired through the multiplication; a transmission line estimating unit that estimates a transfer function of a transmission line using an adaptive nonlinear digital filter on the basis of a symbol array representing a state of the transmission line; an addition comparison processing unit that calculates a minimum value of a distance function in a Viterbi algorithm on the basis of a metric that is calculated on the basis of the output of the transmission line shortening unit and the transfer function; and a path tracing-back determination unit that performs symbol determination by tracing back a trellis path in the Viterbi algorithm on the basis of the minimum value of the distance function.

An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.

A method for tunning high speed link parameters for cables with a transceiver at each end includes transmitting, in response to establishing a link, an eye pattern bit sequence from a first computing device to a second computing device over a cable with a transceiver connected to each end of the cable. Establishing the link includes establishing a communication link over the cable between the first computing device and the second computing device. The method includes receiving an eye pattern quality message from the second computing device using a device discovery protocol. The eye pattern quality message includes quality information of a received waveform corresponding to the transmitted eye pattern bit sequence. The method includes adjusting transmission parameters for transmission over the cable in response to the quality information, and retransmitting the eye pattern bit sequence using the adjusted transmission parameters.