Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

An equalizer circuit includes: a pair of input terminals: a differential amplification circuit outputs, to a pair of output terminals, first signals obtained by amplifying a difference in levels of input signals supplied to the pair of input terminals; and a differential differentiation amplification circuit that outputs, to the pair of output terminals, second signals obtained by amplifying a time-varying change in the difference in the levels of the input signals supplied to the pair of input terminals.

A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.

An information handling system may include a plurality of communication destinations, a communication source, a single-source/multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a communication destination respective to such branch, and a logic device communicatively coupled to the communication source and the single-source/multi-destination cable and configured to communicate to each of the plurality of branches both analog source identifying information and digital source identifying information regarding the communication source.

A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

One aspect of the present disclosure relates to a signal generating method for generating a visible light signal. A signal generating method includes: a step SD11 of determining, as a method for transmitting a visible light signal from a transmitter, one of a single-frame transmitting method for transmitting data as one frame and a multiple-frame transmitting method for transmitting the data while dividing the data into a plurality of frames; a step SD12 of, when the multiple-frame transmitting method is determined, generating partition type information indicating a type of data to be transmitted, and generating combination data by adding the partition type information to the data to be transmitted; a step SD13 of generating the plurality of frames each of which includes each of a plurality of data parts by dividing the combination data into the plurality of data parts; and a step SD14 of generating the visible light signal by adding a preamble to a head of each of the plurality of frames.

One aspect of the present disclosure relates to a signal generating method for generating a visible light signal. A signal generating method includes: a step SD11 of determining, as a method for transmitting a visible light signal from a transmitter, one of a single-frame transmitting method for transmitting data as one frame and a multiple-frame transmitting method for transmitting the data while dividing the data into a plurality of frames; a step SD12 of, when the multiple-frame transmitting method is determined, generating partition type information indicating a type of data to be transmitted, and generating combination data by adding the partition type information to the data to be transmitted; a step SD13 of generating the plurality of frames each of which includes each of a plurality of data parts by dividing the combination data into the plurality of data parts; and a step SD14 of generating the visible light signal by adding a preamble to a head of each of the plurality of frames.

A physical layer transceiver for a data channel includes receiver circuitry configured to receive signals on the data channel, transmit circuitry configured to transmit signals onto the data channel, and adaptive filter circuitry coupled to the receiver circuitry and the transmit circuitry and configured to filter the data channel by operating on input frequency-domain data samples to output filtered data samples. The adaptive filter circuitry includes error sample generation circuitry configured to generate error samples representing a difference between a target response and the filtered data samples, arithmetic-only circuitry configured to approximate a windowing function to operate on the error samples, and output sample generation circuitry configured to operate on windowed error samples to provide the output filtered data samples. The comparison circuitry may be configured for time-domain operation and may further be configured to transform the error signals into frequency-domain error signals.

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.